公开(公告)号：US07227265B2

公开(公告)日：2007-06-05

申请号：US10810719

申请日：2004-03-29

申请人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Christopher C. Parks ,  Soon-Cheon Seo ,  Andrew H. Simon ,  Erick G. Walton

发明人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Christopher C. Parks ,  Soon-Cheon Seo ,  Andrew H. Simon ,  Erick G. Walton

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/024 ,  C25D5/18 ,  C25D7/123 ,  H01L21/76877

摘要： Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 μm and via openings filled with electroplated copper than is substantially free of internal seams or voids.

摘要翻译： 使用包含溶解的铜盐的电镀铜浴获得至少基本上不含内部接缝或空隙的铜导体的互连结构，其中盐的浓度为酸的至少约0.4摩尔浓度至高达约0.5摩尔浓度。 还提供了具有大于约3的宽高比和小于约0.275μm的宽度的铜镶嵌结构以及填充有电镀铜的通孔，基本上不含内部接缝或空隙。

公开(公告)号：US07678258B2

公开(公告)日：2010-03-16

申请号：US10615794

申请日：2003-07-10

申请人： Panayotis Andricacos ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Keith T. Kwietniak ,  Peter S. Locke ,  Darryl D. Restaino ,  Soon-Cheon Seo ,  Philippe M. Vereecken ,  Erick G. Walton

发明人： Panayotis Andricacos ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Keith T. Kwietniak ,  Peter S. Locke ,  Darryl D. Restaino ,  Soon-Cheon Seo ,  Philippe M. Vereecken ,  Erick G. Walton

IPC分类号： C25D5/00

CPC分类号： C23C18/1617 ,  C23C18/1683 ,  C25D21/12 ,  C25D21/18

摘要： An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

摘要翻译： 公开了一种稳定湿化学浴的改进方法。 通常，这种浴用于处理工件的工艺中，例如用于将金属电镀到基底上的电镀工艺。 特别地，本发明涉及镀铜浴。 更具体地说，本发明涉及镀铜浴的稳定性。 更具体地，本发明涉及通过监测铜电镀浴中有害副产物的积累来防止空隙形成。

公开(公告)号：US06974531B2

公开(公告)日：2005-12-13

申请号：US10269956

申请日：2002-10-15

申请人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Michael Lane ,  Sandra G. Malhotra ,  Fenton Read McFeely ,  Conal Murray ,  Kenneth P. Rodbell ,  Philippe M. Vereecken

发明人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Michael Lane ,  Sandra G. Malhotra ,  Fenton Read McFeely ,  Conal Murray ,  Kenneth P. Rodbell ,  Philippe M. Vereecken

IPC分类号： C25D5/18 ,  C25D7/12 ,  B32B15/00

CPC分类号： C25D5/18 ,  C25D7/12 ,  Y10S428/926 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12771 ,  Y10T428/12778 ,  Y10T428/12903

摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

公开(公告)号：US06592747B2

公开(公告)日：2003-07-15

申请号：US09881817

申请日：2001-06-18

申请人： Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke

发明人： Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke

IPC分类号： G01N2742

CPC分类号： G01N31/164 ,  G01N27/42

摘要： Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.

摘要翻译： 通过用硫酸和盐酸和任选的铜盐稀释浴的样品来监测铜电镀浴中的有机添加剂。 稀释液提供具有常规浓度的铜离子，硫酸和盐酸的浴液; 并将样品中原始值的1 / X的有机添加剂的浓度调节到其中; 其中X是稀释因子。 CVS技术用于确定有机添加剂的浓度。

公开(公告)号：US06331237B1

公开(公告)日：2001-12-18

申请号：US09387856

申请日：1999-09-01

申请人： Panayotis C. Andricacos ,  W. Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Cyprian E. Uzoh

发明人： Panayotis C. Andricacos ,  W. Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Cyprian E. Uzoh

IPC分类号： C25D2106

CPC分类号： C25D7/123 ,  C25D5/003 ,  C25D21/12 ,  C25D21/18

摘要： A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.

摘要翻译： 通过电镀液减少种子层的蚀刻的方法。 在将具有种子层的半导体晶片引入电镀液之前，电镀液的蚀刻功率降低。

公开(公告)号：US07863189B2

公开(公告)日：2011-01-04

申请号：US11620423

申请日：2007-01-05

申请人： Veeraraghaven S. Basker ,  John Michael Cotte ,  Hariklia Deligianni ,  John Ulrich Knickerbocker ,  Keith T. Kwietniak

发明人： Veeraraghaven S. Basker ,  John Michael Cotte ,  Hariklia Deligianni ,  John Ulrich Knickerbocker ,  Keith T. Kwietniak

IPC分类号： H01L21/44

CPC分类号： H01L23/433 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/481 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00

摘要： Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with low defect density. In particular, methods are provided which enable fabrication of silicon carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.

摘要翻译： 提供了用于制造具有导电通孔的硅载体的方法，其允许高产量制造具有低缺陷密度的硅载体。 特别地，提供了这样的方法，其能够制造具有通孔直径的硅载体，其直径为小于10微米至大于300微米的垂直厚度，其垂直厚度小于10微米至大于300微米，这对于在生产期间的热机械应力是坚固的 显着地最小化硅，绝缘体，衬里和导体材料之间的通孔侧壁界面处的热机械运动。

公开(公告)号：US06921978B2

公开(公告)日：2005-07-26

申请号：US10249799

申请日：2003-05-08

申请人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

发明人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

IPC分类号： H01L21/312 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

公开(公告)号：US07101784B2

公开(公告)日：2006-09-05

申请号：US11125549

申请日：2005-05-10

申请人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

发明人： Lawrence A. Clevenger ,  Stephen E. Greco ,  Keith T. Kwietniak ,  Soon-Cheon Seo ,  Chih-Chao Yang ,  Yun-Yu Wang ,  Kwong H. Wong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76835 ,  H01L21/76856 ,  H01L2221/1036

摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

摘要翻译： 本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔 衬垫。 衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。 在等离子体处理期间，等离子体通过衬垫而不影响衬垫。 在等离子体处理之后，可以沉积另外的衬里材料。 此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。 该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。 绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

公开(公告)号：US20080164573A1

公开(公告)日：2008-07-10

申请号：US11620423

申请日：2007-01-05

申请人： Veeraraghaven S. Basker ,  John Michael Cotte ,  Hariklia Deligianni ,  John Ulrich Knickerbocker ,  Keith T. Kwietniak

发明人： Veeraraghaven S. Basker ,  John Michael Cotte ,  Hariklia Deligianni ,  John Ulrich Knickerbocker ,  Keith T. Kwietniak

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L23/433 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/055 ,  H01L23/481 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00

摘要： Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with, low defect density. In particular, methods are provided which enable fabrication of silicon, carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.

摘要翻译： 提供了用于制造具有导电通孔的硅载体的方法，其允许以低缺陷密度高产量制造硅载体。 特别地，提供了能够制造硅的方法，具有通孔直径，例如直径为1至10微米，垂直厚度小于10微米至大于300微米，这对于生产过程中的热机械应力是坚固的 以显着地最小化硅，绝缘体，衬里和导体材料之间的通孔侧壁界面处的热机械运动。