公开(公告)号：US07227265B2

公开(公告)日：2007-06-05

申请号：US10810719

申请日：2004-03-29

申请人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Christopher C. Parks ,  Soon-Cheon Seo ,  Andrew H. Simon ,  Erick G. Walton

发明人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Christopher C. Parks ,  Soon-Cheon Seo ,  Andrew H. Simon ,  Erick G. Walton

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/024 ,  C25D5/18 ,  C25D7/123 ,  H01L21/76877

摘要： Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 μm and via openings filled with electroplated copper than is substantially free of internal seams or voids.

摘要翻译： 使用包含溶解的铜盐的电镀铜浴获得至少基本上不含内部接缝或空隙的铜导体的互连结构，其中盐的浓度为酸的至少约0.4摩尔浓度至高达约0.5摩尔浓度。 还提供了具有大于约3的宽高比和小于约0.275μm的宽度的铜镶嵌结构以及填充有电镀铜的通孔，基本上不含内部接缝或空隙。

公开(公告)号：US07678258B2

公开(公告)日：2010-03-16

申请号：US10615794

申请日：2003-07-10

申请人： Panayotis Andricacos ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Keith T. Kwietniak ,  Peter S. Locke ,  Darryl D. Restaino ,  Soon-Cheon Seo ,  Philippe M. Vereecken ,  Erick G. Walton

发明人： Panayotis Andricacos ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Keith T. Kwietniak ,  Peter S. Locke ,  Darryl D. Restaino ,  Soon-Cheon Seo ,  Philippe M. Vereecken ,  Erick G. Walton

IPC分类号： C25D5/00

CPC分类号： C23C18/1617 ,  C23C18/1683 ,  C25D21/12 ,  C25D21/18

摘要： An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

摘要翻译： 公开了一种稳定湿化学浴的改进方法。 通常，这种浴用于处理工件的工艺中，例如用于将金属电镀到基底上的电镀工艺。 特别地，本发明涉及镀铜浴。 更具体地说，本发明涉及镀铜浴的稳定性。 更具体地，本发明涉及通过监测铜电镀浴中有害副产物的积累来防止空隙形成。

公开(公告)号：US06974531B2

公开(公告)日：2005-12-13

申请号：US10269956

申请日：2002-10-15

申请人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Michael Lane ,  Sandra G. Malhotra ,  Fenton Read McFeely ,  Conal Murray ,  Kenneth P. Rodbell ,  Philippe M. Vereecken

发明人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Michael Lane ,  Sandra G. Malhotra ,  Fenton Read McFeely ,  Conal Murray ,  Kenneth P. Rodbell ,  Philippe M. Vereecken

IPC分类号： C25D5/18 ,  C25D7/12 ,  B32B15/00

CPC分类号： C25D5/18 ,  C25D7/12 ,  Y10S428/926 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12771 ,  Y10T428/12778 ,  Y10T428/12903

摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

公开(公告)号：US06270646B1

公开(公告)日：2001-08-07

申请号：US09473909

申请日：1999-12-28

申请人： Erick Gregory Walton ,  Dean S. Chung ,  Lara Sandra Collins ,  William E. Corbin, Jr. ,  Hariklia Deligianni ,  Daniel Charles Edelstein ,  James E. Fluegel ,  Josef Warren Korejwa ,  Peter S. Locke ,  Cyprian Emeka Uzoh

发明人： Erick Gregory Walton ,  Dean S. Chung ,  Lara Sandra Collins ,  William E. Corbin, Jr. ,  Hariklia Deligianni ,  Daniel Charles Edelstein ,  James E. Fluegel ,  Josef Warren Korejwa ,  Peter S. Locke ,  Cyprian Emeka Uzoh

IPC分类号： C25D522

CPC分类号： C25D17/14 ,  C25D5/06

摘要： A metal plating apparatus is described which includes a compressible member having a conductive surface covering substantially all of the surface of the substrate to be plated. The plating current is thereby transmitted over a wide area of the substrate, rather than a few localized contact points. The compressible member is porous so as to absorb the plating solution and transmit the plating solution to the substrate. The wafer and compressible member may rotate with respect to each other. The compressible member may be at cathode potential or may be a passive circuit element.

摘要翻译： 描述了一种金属电镀装置，其包括具有覆盖待镀基板的基本上所有表面的导电表面的可压缩构件。 因此，电镀电流在衬底的广泛区域上传输，而不是几个局部接触点。 可压缩构件是多孔的，以便吸收电镀液并将电镀液传输到基底。 晶片和可压缩构件可以相对于彼此旋转。 可压缩构件可以处于阴极电位，或者可以是无源电路元件。

公开(公告)号：US20100051474A1

公开(公告)日：2010-03-04

申请号：US12548893

申请日：2009-08-27

申请人： Panayotis C. Andricacos ,  Caliopi Andricacos ,  Donald F. Canaperi ,  Emanuel I. Cooper ,  John M. Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel C. Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew P. Mansson ,  Erick G. Walton ,  Alan C. West

发明人： Panayotis C. Andricacos ,  Caliopi Andricacos ,  Donald F. Canaperi ,  Emanuel I. Cooper ,  John M. Cotte ,  Hariklia Deligianni ,  Laertis Economikos ,  Daniel C. Edelstein ,  Silvia Franz ,  Balasubramanian Pranatharthiharan ,  Mahadevaiyer Krishnan ,  Andrew P. Mansson ,  Erick G. Walton ,  Alan C. West

IPC分类号： B23H5/06

CPC分类号： C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

摘要翻译： 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：US06709562B1

公开(公告)日：2004-03-23

申请号：US09348632

申请日：1999-07-06

申请人： Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  John Owen Dukovic ,  Daniel Charles Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth Parker Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

发明人： Panayotis Constantinou Andricacos ,  Hariklia Deligianni ,  John Owen Dukovic ,  Daniel Charles Edelstein ,  Wilma Jean Horkans ,  Chao-Kun Hu ,  Jeffrey Louis Hurd ,  Kenneth Parker Rodbell ,  Cyprian Emeka Uzoh ,  Kwong-Hon Wong

IPC分类号： C25D712

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D7/123 ,  H01L21/76877

摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

摘要翻译： 描述了用于制造用于集成电路芯片的亚微米互连结构的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。 以这种方式使用电镀Cu的结构的电迁移电阻优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

公开(公告)号：US06224690B1

公开(公告)日：2001-05-01

申请号：US08614984

申请日：1996-03-12

申请人： Panayotis Constantinou Andricacos ,  Madhav Datta ,  Hariklia Deligianni ,  Wilma Jean Horkans ,  Sung Kwon Kang ,  Keith Thomas Kwietniak ,  Gangadhara Swami Mathad ,  Sampath Purushothaman ,  Leathen Shi ,  Ho-Ming Tong

发明人： Panayotis Constantinou Andricacos ,  Madhav Datta ,  Hariklia Deligianni ,  Wilma Jean Horkans ,  Sung Kwon Kang ,  Keith Thomas Kwietniak ,  Gangadhara Swami Mathad ,  Sampath Purushothaman ,  Leathen Shi ,  Ho-Ming Tong

IPC分类号： C22C700

CPC分类号： C22C13/02 ,  B23K2035/008 ,  B32B15/01 ,  C22C13/00 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/30107 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/01026

摘要： An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

摘要翻译： 适用于将微电子电路芯片连接到封装件的互连结构由本发明提供。 特别地，本发明涉及通常称为C4（可控崩溃芯片连接）的区域阵列或倒装芯片技术。 该结构包括沉积在钝化衬底（例如，硅晶片）上的粘附/阻挡层，任选附加的粘合层，选自Ni，Co，Fe，NiFe，NiCo，CoFe的金属的可焊层 和NiCoFe，以及包含锡作为主要成分的无铅焊球和选自Bi，Ag和Sb的一种或多种合金元素，并且还可任选地包括一种或多种选自以下的元素： 的Zn，In，Ni，Co和Cu。

公开(公告)号：US07190079B2

公开(公告)日：2007-03-13

申请号：US11265302

申请日：2005-11-03

申请人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

发明人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

摘要翻译： 通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。 提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

公开(公告)号：US20100047990A1

公开(公告)日：2010-02-25

申请号：US12612743

申请日：2009-11-05

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01L21/02

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

摘要翻译： 一种形成电感器的方法。 该方法包括：（a）在基板的顶表面上形成电介质层; （a）之后，（b）在介电层中形成下沟槽; （b）之后，（c）在介电层的顶表面上形成抗蚀剂层; 在（c）之后，（d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; （d）之后，（e）完全填充下沟槽并且用导体至少部分地填充上沟槽以形成电感器。

公开(公告)号：US07008871B2

公开(公告)日：2006-03-07

申请号：US10611931

申请日：2003-07-03

申请人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

发明人： Panayotis C. Andricacos ,  Shyng-Tsong Chen ,  John M. Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe M. Vereecken

IPC分类号： H01L21/44

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

摘要翻译： 通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。 提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。