公开(公告)号：US10236715B2

公开(公告)日：2019-03-19

申请号：US15229122

申请日：2016-08-05

申请人： Dexin Liang

发明人： Dexin Liang

IPC分类号： H02J7/00 ,  H02J9/00 ,  H02J9/06 ,  H02J1/10

摘要： The present invention provides a switch power circuit with a backup battery for power supply, comprising an input rectifier module, an PWM switch control module, a transformer module, an output rectifier diode, a negative feedback module, a backup battery, an isolation diode unit and a zener diode; the anode of the output rectifier diode is connected with the positive output end of the transformer unit, the cathode of the output rectifier diode is connected with the cathode of the isolation diode unit, the anode of the isolation diode unit is connected with the anode of the backup battery, the cathode of the backup battery is connected with the negative output end of the transformer module; the cathode of the zener diode is connected between the cathode of the isolation diode unit and the cathode of the output rectifier diode; one end of the negative feedback module is connected with the anode of the zener diode, and the other end of the negative feedback module is connected with the control port of the PWM switch control module. The present invention has beneficial effects of reducing output consumption of switch power supply and increasing conversion efficiency of switch power supply.

公开(公告)号：USRE42457E1

公开(公告)日：2011-06-14

申请号：US12629769

申请日：2009-12-02

申请人： Lily Zhao ,  Dexin Liang

发明人： Lily Zhao ,  Dexin Liang

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0219 ,  H05K3/3436 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： The present invention includes an integrated circuit package, a ball-grid array integrated circuit package, a method of packaging an integrated circuit, and a method of forming an integrated circuit package. According to one aspect, the present invention provides an integrated circuit package including a substrate including a first surface, a second surface and a plurality of conductors, the first surface includes a plurality of conductive pads adapted to couple with a plurality of corresponding bond pads of a semiconductor die, and the conductors being configured to couple the conductive pads with the second surface; and a plurality of conductive bumps coupled with the second surface of the substrate and electrically coupled with respective conductors, the conductive bumps being formed in an array including a plurality of power bumps and signal bumps, and the signal bumps being individually positioned immediately adjacent at least one power bump. One method of packaging an integrated circuit includes providing a semiconductor die including a plurality of bond pads; providing a package substrate including a plurality of conductive bumps including plural power bumps and plural signal bumps; arranging individual signal bumps to be immediately adjacent at least one power bump; and electrically coupling the bond pads of the semiconductor die with respective conductive bumps.

摘要翻译： 本发明包括集成电路封装，球栅阵列集成电路封装，封装集成电路的方法以及形成集成电路封装的方法。 根据一个方面，本发明提供了一种集成电路封装，其包括包括第一表面，第二表面和多个导体的基板，所述第一表面包括多个导电焊盘，其适于与多个对应的焊盘焊接 半导体管芯，并且所述导体被配置为将所述导电焊盘与所述第二表面耦合; 以及与所述基板的所述第二表面耦合并与相应导体电耦合的多个导电凸块，所述导电凸块形成为包括多个功率凸起和信号凸起的阵列，并且所述信号凸块分别紧邻至少 一个电源碰撞。 封装集成电路的一种方法包括提供包括多个接合焊盘的半导体管芯; 提供包括多个导电凸块的封装基板，所述导电凸块包括多个电源凸块和多个信号凸块; 布置各个信号凸块以紧邻至少一个电源凸块; 并将半导体管芯的接合焊盘与相应的导电凸块电耦合。

公开(公告)号：US5639696A

公开(公告)日：1997-06-17

申请号：US595022

申请日：1996-01-31

申请人： Dexin Liang ,  Mark R. Schneider

发明人： Dexin Liang ,  Mark R. Schneider

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H05K3/3436 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K2201/10477 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/159 ,  H05K2203/306 ,  Y02P70/613

摘要： An integrated circuit is mounted on and interconnected with a circuit board by an array of electrically conductive columns. The assembly is fabricated by initially interconnecting the integrated circuit and the circuit board with an array of reflowable electrically conductive solder balls that correspond to the columns respectively. The circuit board is held with the integrated circuit extending downwardly therefrom. Sufficient heat is applied to cause the solder balls to reflow. The integrated circuit is pulled downwardly away from the circuit board by gravity such that the balls are stretched to form the columns, and the assembly is allowed to cool such that the columns solidify. A fixture may be provided against which the integrated circuit abuts after it has moved away from the circuit board by a predetermined distance such that the columns have a precisely determined height.

摘要翻译： 集成电路通过导电柱阵列安装在电路板上并与电路板互连。 通过首先将集成电路和电路板与分别对应于列的可回流导电焊球的阵列互连来制造组件。 电路板保持有从其向下延伸的集成电路。 施加足够的热量使焊球回流。 通过重力将集成电路向下拉离电路板，使得球被拉伸以形成柱，并且允许组件冷却，使得柱固化。 可以提供固定装置，其在集成电路已经从电路板移开预定距离之后抵靠着固定装置，使得列具有精确确定的高度。

公开(公告)号：US06207476B1

公开(公告)日：2001-03-27

申请号：US09330241

申请日：1999-06-10

申请人： Lily Zhao ,  Dexin Liang

发明人： Lily Zhao ,  Dexin Liang

IPC分类号： H01L2144

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0219 ,  H05K3/3436 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： The present invention includes an integrated circuit package, a ball-grid array integrated circuit package, a method of packaging an integrated circuit, and a method of forming an integrated circuit package. According to one aspect, the present invention provides an integrated circuit package including a substrate including a first surface, a second surface and a plurality of conductors, the first surface includes a plurality of conductive pads adapted to couple with a plurality of corresponding bond pads of a semiconductor die, and the conductors being configured to couple the conductive pads with the second surface; and a plurality of conductive bumps coupled with the second surface of the substrate and electrically coupled with respective conductors, the conductive bumps being formed in an array including a plurality of power bumps and signal bumps, and the signal bumps being individually positioned immediately adjacent at least one power bump. One method of packaging an integrated circuit includes providing a semiconductor die including a plurality of bond pads; providing a package substrate including a plurality of conductive bumps including plural power bumps and plural signal bumps; arranging individual signal bumps to be immediately adjacent at least one power bump; and electrically coupling the bond pads of the semiconductor die with respective conductive bumps.

摘要翻译： 本发明包括集成电路封装，球栅阵列集成电路封装，封装集成电路的方法以及形成集成电路封装的方法。 根据一个方面，本发明提供了一种集成电路封装，其包括包括第一表面，第二表面和多个导体的基板，所述第一表面包括多个导电焊盘，其适于与多个对应的焊盘焊接 半导体管芯，并且所述导体被配置为将所述导电焊盘与所述第二表面耦合; 以及与所述基板的所述第二表面耦合并与相应导体电耦合的多个导电凸块，所述导电凸块形成为包括多个功率凸起和信号凸起的阵列，并且所述信号凸块分别紧邻至少 一个电源碰撞。 封装集成电路的一种方法包括提供包括多个接合焊盘的半导体管芯; 提供包括多个导电凸块的封装基板，所述导电凸块包括多个电源凸块和多个信号凸块; 布置各个信号凸块以紧邻至少一个电源凸块; 并将半导体管芯的接合焊盘与相应的导电凸块电耦合。

公开(公告)号：US5688606A

公开(公告)日：1997-11-18

申请号：US633256

申请日：1996-04-18

申请人： Deepak Mahulikar ,  Efraim Sagiv ,  Arvind Parthasarathi ,  Satish Jalota ,  Andrew J. Brock ,  Michael A. Holmes ,  Jeffrey M. Schlater ,  German J. Ramirez ,  Dexin Liang

发明人： Deepak Mahulikar ,  Efraim Sagiv ,  Arvind Parthasarathi ,  Satish Jalota ,  Andrew J. Brock ,  Michael A. Holmes ,  Jeffrey M. Schlater ,  German J. Ramirez ,  Dexin Liang

IPC分类号： C25D11/04 ,  H01L23/02 ,  H01L23/04 ,  H01L23/06 ,  H01L23/14 ,  H05K1/05 ,  B32B15/00 ,  B21D39/00 ,  B32B3/00 ,  C25D5/18

CPC分类号： H05K1/056 ,  H01L23/142 ,  H05K1/053 ,  H01L2224/16225 ,  H01L2924/01327 ,  Y10T428/12493 ,  Y10T428/12556 ,  Y10T428/12736 ,  Y10T428/24917

摘要： There is provided an anodizable aluminum substrate having an increased breakdown voltage. The increase in breakdown voltage is achieved by selecting an appropriate aluminum alloy and appropriate processing parameters. Sealing the anodic film increases the breakdown voltage by decreasing corrosion. A preferred sealant is an epoxy cresol novolac having a low room temperature viscosity that cures to a highly cross-linked polymer.

摘要翻译： 提供了具有增加的击穿电压的阳极氧化铝基板。 通过选择适当的铝合金和适当的加工参数来实现击穿电压的增加。 密封阳极膜通过减少腐蚀来增加击穿电压。 优选的密封剂是具有低固化至高度交联的聚合物的低室温粘度的环氧甲酚酚醛清漆。

公开(公告)号：US5534356A

公开(公告)日：1996-07-09

申请号：US427921

申请日：1995-04-26

申请人： Deepak Mahulikar ,  Efraim Sagiv ,  Arvind Parthasarathi ,  Satish Jalota ,  Andrew J. Brock ,  Michael A. Holmes ,  Jeffrey M. Schlater ,  German J. Ramirez ,  Dexin Liang

发明人： Deepak Mahulikar ,  Efraim Sagiv ,  Arvind Parthasarathi ,  Satish Jalota ,  Andrew J. Brock ,  Michael A. Holmes ,  Jeffrey M. Schlater ,  German J. Ramirez ,  Dexin Liang

IPC分类号： C25D11/04 ,  H01L23/02 ,  H01L23/04 ,  H01L23/06 ,  H01L23/14 ,  H05K1/05 ,  B32B9/00

CPC分类号： H05K1/056 ,  H01L23/142 ,  H05K1/053 ,  H01L2224/16225 ,  H01L2924/01327 ,  Y10T428/12493 ,  Y10T428/12556 ,  Y10T428/12736 ,  Y10T428/24917

摘要： There is provided an anodizable aluminum substrate having an increased breakdown voltage. The increase in breakdown voltage is achieved by selecting an appropriate aluminum alloy and appropriate processing parameters. Sealing the anodic film increases the breakdown voltage by decreasing corrosion. A preferred sealant is an epoxy cresol novolac having a low room temperature viscosity that cures to a highly cross-linked polymer.

摘要翻译： 提供了具有增加的击穿电压的可阳极氧化的铝基板。 通过选择适当的铝合金和适当的加工参数来实现击穿电压的增加。 密封阳极膜通过减少腐蚀增加击穿电压。 优选的密封剂是具有低固化至高度交联的聚合物的低室温粘度的环氧甲酚酚醛清漆。

公开(公告)号：USRE42332E1

公开(公告)日：2011-05-10

申请号：US12629951

申请日：2009-12-03

申请人： Lily Zhao ,  Dexin Liang

发明人： Lily Zhao ,  Dexin Liang

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0219 ,  H05K3/3436 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： The present invention includes an integrated circuit package, a ball-grid array integrated circuit package, a method of packaging an integrated circuit, and a method of forming an integrated circuit package. According to one aspect, the present invention provides an integrated circuit package including a substrate including a first surface, a second surface and a plurality of conductors, the first surface includes a plurality of conductive pads adapted to couple with a plurality of corresponding bond pads of a semiconductor die, and the conductors being configured to couple the conductive pads with the second surface; and a plurality of conductive bumps coupled with the second surface of the substrate and electrically coupled with respective conductors, the conductive bumps being formed in an array including a plurality of power bumps and signal bumps, and the signal bumps being individually positioned immediately adjacent at least one power bump. One method of packaging an integrated circuit includes providing a semiconductor die including a plurality of bond pads; providing a package substrate including a plurality of conductive bumps including plural power bumps and plural signal bumps; arranging individual signal bumps to be immediately adjacent at least one power bump; and electrically coupling the bond pads of the semiconductor die with respective conductive bumps.

摘要翻译： 本发明包括集成电路封装，球栅阵列集成电路封装，封装集成电路的方法以及形成集成电路封装的方法。 根据一个方面，本发明提供了一种集成电路封装，其包括包括第一表面，第二表面和多个导体的基板，所述第一表面包括多个导电焊盘，其适于与多个对应的焊盘焊接 半导体管芯，并且所述导体被配置为将所述导电焊盘与所述第二表面耦合; 以及与所述基板的所述第二表面耦合并与相应导体电耦合的多个导电凸块，所述导电凸块形成为包括多个功率凸起和信号凸起的阵列，并且所述信号凸块分别紧邻至少 一个电源碰撞。 封装集成电路的一种方法包括提供包括多个接合焊盘的半导体管芯; 提供包括多个导电凸块的封装基板，所述导电凸块包括多个电源凸块和多个信号凸块; 布置各个信号凸块以紧邻至少一个电源凸块; 并将半导体管芯的接合焊盘与相应的导电凸块电耦合。

公开(公告)号：US06222260B1

公开(公告)日：2001-04-24

申请号：US09074564

申请日：1998-05-07

申请人： Dexin Liang ,  Ray Killorn

发明人： Dexin Liang ,  Ray Killorn

IPC分类号： H01L2352

CPC分类号： H01L23/642 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A flat, thin decoupling capacitor is disposed inside an integrated circuit device in a coplanar relationship with a semiconductor chip and a bonding element. When connected to the power and ground plane of a device substrate or in a leadframe device, the decoupling capacitor is positioned close to the semiconductor chip to substantially reduce ground bounce and crosstalk from the semiconductor chip. When the decoupling capacitor is positioned to locate the semiconductor chip between itself and the device substrate or leadframe device, the decoupling capacitor shields electromagnetic interference from the semiconductor chip.

摘要翻译： 扁平的薄去耦电容器设置在与半导体芯片和接合元件共面关系的集成电路器件的内部。 当连接到器件基板或引线框架器件的电源和接地平面时，去耦电容器位于靠近半导体芯片的位置，从而大大减少了来自半导体芯片的接地反弹和串扰。 当去耦电容器定位成将半导体芯片定位在其本身与器件衬底或引线框架器件之间时，去耦电容屏蔽来自半导体芯片的电磁干扰。

公开(公告)号：US5455386A

公开(公告)日：1995-10-03

申请号：US181687

申请日：1994-01-14

申请人： George A. Brathwaite ,  German J. Ramirez ,  Michael A. Holmes ,  Paul R. Hoffman ,  Dexin Liang

发明人： George A. Brathwaite ,  German J. Ramirez ,  Michael A. Holmes ,  Paul R. Hoffman ,  Dexin Liang

IPC分类号： H01L23/02 ,  H01L23/10 ,  H01L23/367

CPC分类号： H01L23/10 ,  H01L23/3675 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16151 ,  H01L2924/16152

摘要： There is disclosed an adhesively sealed electronic package in which a compensation apparatus is provided for excess adhesive. As a result, excess adhesive does not extend beyond the package perimeter, squeeze-out, or travel along the inner lead fingers interfering with wire bonding. The compensation is a chamfer on the peripheral edges and/or interior edges of the package base component and cover component.

摘要翻译： 公开了一种粘合密封的电子封装，其中为多余的粘合剂提供补偿装置。 因此，多余的粘合剂不会超过包装周长，挤出或沿着内部引线指引而妨碍引线接合。 补偿是在封装基座部件和盖部件的外围边缘和/或内部边缘上的倒角。

公开(公告)号：US5239131A

公开(公告)日：1993-08-24

申请号：US912456

申请日：1992-07-13

申请人： Paul R. Hoffman ,  Linda E. Strauman ,  Dexin Liang ,  Sonny S. Pareno ,  German J. Ramirez

发明人： Paul R. Hoffman ,  Linda E. Strauman ,  Dexin Liang ,  Sonny S. Pareno ,  German J. Ramirez

IPC分类号： H05K5/00 ,  H01L21/48 ,  H01L23/10 ,  H01L23/22 ,  H01L23/50

CPC分类号： H01L24/32 ,  H01L21/4839 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/20752

摘要： There is provided an electronic package assembly having a die attach paddle bonded to the package base by a compliant adhesive. A recessed channel formed in the base is partially overlapped by the die attach paddle. During package sealing, excess adhesive accumulates in the recessed channel, eliminating bridging of the adhesive to the leadframe.

摘要翻译： 提供了一种电子封装组件，其具有通过顺应性粘合剂结合到封装基座的管芯附接焊盘。 形成在基座中的凹陷通道部分地与管芯连接板重叠。 在封装密封期间，多余的粘合剂积聚在凹槽中，消除了粘合剂与引线框架的桥接。