公开(公告)号：US08658467B2

公开(公告)日：2014-02-25

申请号：US12929703

申请日：2011-02-09

Applicant: Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Yuan Jing Li ,  Jong Yun Lee

Inventor： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Yuan Jing Li ,  Jong Yun Lee

IPC: H01L21/00

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.

Abstract translation: 层叠晶片级封装的制造方法包括：准备基板; 在所述基板上形成导电层; 在导电层上形成芯片连接焊盘和内部连接焊盘; 形成连接到内部连接焊盘的焊球; 将半导体芯片安装在所述导电层上以连接到所述芯片连接焊盘; 形成密封构件以密封焊球和半导体芯片; 将衬底与导电层分离; 通过蚀刻导电层形成重排布线层; 在所述重排布线层上形成外部连接; 在所述密封构件中形成接触孔以暴露所述焊球; 并且堆叠要电连接到通过接触孔暴露的焊料球的电子部件。

公开(公告)号：US20120067636A1

公开(公告)日：2012-03-22

申请号：US13233851

申请日：2011-09-15

Applicant: Jin Gu KIM ,  Mi Jin KIM ,  Young Ho KIM ,  Seung Wook PARK ,  Hee Kon LEE ,  Young Do KWEON

Inventor： Jin Gu KIM ,  Mi Jin KIM ,  Young Ho KIM ,  Seung Wook PARK ,  Hee Kon LEE ,  Young Do KWEON

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K3/4694 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/3436 ,  H05K2203/041 ,  H01L2224/0401

Abstract: Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.

Abstract translation: 本发明公开了一种嵌入式嵌入式印刷电路板，包括：基板，其具有在其一面形成并在基板的厚度方向上具有预定高度的空腔; 插入器，其设置在所述空腔中并且包括布线区域和绝缘区域; 以及形成在所述基板中并且包括与所述布线区域的一侧连接的连接图案的电路层。 嵌入式嵌入式印刷电路板的优点在于，嵌入在衬底中，从而可以减小半导体封装的厚度，从而跟上半导体封装变窄的趋势。

公开(公告)号：US20110198749A1

公开(公告)日：2011-08-18

申请号：US12929783

申请日：2011-02-15

Applicant: Hee Kon Lee ,  Ju Pyo Hong ,  Eun Kyung Jeon ,  Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim

Inventor： Hee Kon Lee ,  Ju Pyo Hong ,  Eun Kyung Jeon ,  Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim

IPC: H01L23/52 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/24226 ,  H01L2224/73267 ,  H01L2924/01012 ,  H01L2924/15174 ,  H01L2924/15311

Abstract: Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip comprising a chip pad, and a rerouting layer disposed on the semiconductor chip and including a metal interconnection electrically connected to the chip pad and a partial oxidation region formed by the oxidation of metal and insulating the metal interconnection.

Abstract translation: 提供一种半导体芯片封装及其制造方法。 该半导体芯片封装包括一个包括芯片焊盘的半导体芯片和一个设置在半导体芯片上的重新布线层，并且包括与芯片焊盘电连接的金属互连和通过金属的氧化形成的绝缘金属互连的部分氧化区。

公开(公告)号：US20110156241A1

公开(公告)日：2011-06-30

申请号：US12712044

申请日：2010-02-24

Applicant: Ju Pyo HONG ,  Young Do Kweon ,  Jin Gu Kim ,  Seung Wook Park ,  Hee Kon Lee

Inventor： Ju Pyo HONG ,  Young Do Kweon ,  Jin Gu Kim ,  Seung Wook Park ,  Hee Kon Lee

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/3128 ,  H01L23/3135 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/24 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed herein are a package substrate and a method of fabricating the same. The package substrate includes a base part that includes a chip, a mold part surrounding the chip, and a connection unit formed inside the mold part to connect the chip to a terminal part formed on the outer surface of the mold part, and a buildup layer that is formed on one surface of the base part on which the terminal part is formed, including the side surfaces of the base part, but includes a circuit layer connected to the terminal part, thereby making it possible to minimize stress applied to chips during a buildup process and easily replace malfunctioning chips.

Abstract translation: 本文公开了封装衬底及其制造方法。 封装基板包括基部，该基部包括芯片，围绕芯片的模具部分和形成在模具部分内的连接单元，以将芯片连接到形成在模具部件的外表面上的端子部分，以及累积层 形成在其上形成有端子部的基部的一个表面上，包括基部的侧表面，但是包括连接到端子部的电路层，从而使得可以最小化在一个 积累过程，轻松替代故障芯片。

公开(公告)号：US20100159646A1

公开(公告)日：2010-06-24

申请号：US12453273

申请日：2009-05-05

Applicant: Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

Inventor： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

IPC: H01L21/78

CPC classification number: H01L21/561 ,  H01L23/24 ,  H01L23/3121 ,  H01L24/94 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.

Abstract translation: 本发明涉及一种制造晶片级封装的方法，包括以下步骤：制备包括形成在底表面上的多个焊盘，位于顶表面上的多个芯片的基板晶片和用于分割芯片的切割线 ; 在焊盘上形成外部连接单元; 通过将衬底定位在衬底晶片上以仅露出切割线，在切割线上涂覆树脂; 去除面具; 通过用密封剂涂覆芯片来封装位于树脂之间的芯片; 去除涂覆在切割线上的树脂; 以及沿着通过将树脂去除单元暴露的切割线切割晶片级封装。

公开(公告)号：US08704350B2

公开(公告)日：2014-04-22

申请号：US12458454

申请日：2009-07-13

Applicant: Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

Inventor： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

Abstract translation: 本发明涉及层叠晶片级封装及其制造方法。 根据本发明的堆叠晶片级封装可以通过在预先接合用于互连的内部连接装置之后执行半导体芯片安装处理，重排布线层形成处理，堆叠处理等来改善堆叠处理中产生的未对准问题 在层叠的电子部件之间形成用于形成重排布线层的导电层，从而提高可靠性和产率，并降低制造成本。

公开(公告)号：US20110201156A1

公开(公告)日：2011-08-18

申请号：US13064878

申请日：2011-04-22

Applicant: Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

Inventor： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

IPC: H01L21/50

CPC classification number: H01L21/561 ,  H01L23/24 ,  H01L23/3121 ,  H01L24/94 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units.

Abstract translation: 一种制造晶片级封装的方法，包括：准备包括形成在底表面上的多个焊盘，位于顶表面上的多个芯片的基板晶片和用于分割芯片的切割线; 在焊盘上形成外部连接单元; 通过将衬底定位在衬底晶片上以仅露出切割线，在切割线上涂覆树脂; 去除面具; 通过用密封剂涂覆芯片来封装位于树脂之间的芯片，并沿着涂覆有树脂的切割线将晶片级封装切割成单元。

公开(公告)号：US07947530B2

公开(公告)日：2011-05-24

申请号：US12453273

申请日：2009-05-05

Applicant: Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

Inventor： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/561 ,  H01L23/24 ,  H01L23/3121 ,  H01L24/94 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.

Abstract translation: 本发明涉及一种制造晶片级封装的方法，包括以下步骤：制备包括形成在底表面上的多个焊盘，位于顶表面上的多个芯片的基板晶片和用于分割芯片的切割线 ; 在焊盘上形成外部连接单元; 通过将衬底定位在衬底晶片上以仅露出切割线，在切割线上涂覆树脂; 去除面具; 通过用密封剂涂覆芯片来封装位于树脂之间的芯片; 去除涂覆在切割线上的树脂; 以及沿着通过将树脂去除单元暴露的切割线切割晶片级封装。

公开(公告)号：US20100117218A1

公开(公告)日：2010-05-13

申请号：US12458454

申请日：2009-07-13

Applicant: Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

Inventor： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/60 ,  H01L23/29

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

Abstract translation: 本发明涉及层叠晶片级封装及其制造方法。 根据本发明的堆叠晶片级封装可以通过在预先接合用于互连的内部连接装置之后执行半导体芯片安装处理，重排布线层形成处理，堆叠处理等来改善堆叠处理中产生的未对准问题 在层叠的电子部件之间形成用于形成重排布线层的导电层，从而提高可靠性和产率，并降低制造成本。

公开(公告)号：US08830689B2

公开(公告)日：2014-09-09

申请号：US13233851

申请日：2011-09-15

Applicant: Jin Gu Kim ,  Mi Jin Park ,  Young Ho Kim ,  Seung Wook Park ,  Hee Kon Lee ,  Young Do Kweon

Inventor： Jin Gu Kim ,  Mi Jin Park ,  Young Ho Kim ,  Seung Wook Park ,  Hee Kon Lee ,  Young Do Kweon

IPC: H05K7/00 ,  H05K1/11 ,  H05K7/02 ,  H01L23/498 ,  H05K3/46 ,  H05K3/34

CPC classification number: H05K3/4694 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/3436 ,  H05K2203/041 ,  H01L2224/0401

Abstract: Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package.

Abstract translation: 本发明公开了一种嵌入式嵌入式印刷电路板，包括：基板，其具有在其一面形成并在基板的厚度方向上具有预定高度的空腔; 插入器，其设置在所述空腔中并且包括布线区域和绝缘区域; 以及形成在所述基板中并且包括与所述布线区域的一侧连接的连接图案的电路层。 嵌入式嵌入式印刷电路板的优点在于，嵌入在衬底中，从而可以减小半导体封装的厚度，从而跟上半导体封装变窄的趋势。