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    UNDERFILL ADHESION MEASUREMENTS AT A MICROSCOPIC SCALE
    2.
    发明申请
    UNDERFILL ADHESION MEASUREMENTS AT A MICROSCOPIC SCALE 有权
    在微观尺度下的不完全粘合测量

    公开(公告)号：US20140030827A1

    公开(公告)日：2014-01-30

    申请号：US13561661

    申请日：2012-07-30

    申请人： Maxime CADOTTE ,  Marie-Claude PAQUET ,  Julien SYLVESTRE

    发明人： Maxime CADOTTE ,  Marie-Claude PAQUET ,  Julien SYLVESTRE

    IPC分类号： H01L21/66

    CPC分类号： H01L22/12 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

    摘要： Methods and systems to method to determine an adhesion force of an underfill material to a chip assembled in a flip-chip module are provided. A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate. The method also includes forming a block from the layer of underfill material. The method further includes measuring a force required to shear the block from a surface of the flip-chip module.

    摘要翻译： 提供了用于确定底部填充材料对组装在倒装芯片组件中的芯片的粘附力的方法和系统。 一种方法包括形成倒装芯片模块，其包括连接到具有附着在芯片和基板上的底层填充材料层的基板的芯片。 该方法还包括从底部填充材料层形成块。 该方法还包括测量从倒装芯片模块的表面切割块所需的力。

    METHOD AND APPARATUS TO MINIMIZE STRESS DURING REFLOW PROCESS
    3.
    发明申请
    METHOD AND APPARATUS TO MINIMIZE STRESS DURING REFLOW PROCESS 审中-公开
    在反射过程中最小化应力的方法和装置

    公开(公告)号：US20090298206A1

    公开(公告)日：2009-12-03

    申请号：US12127895

    申请日：2008-05-28

    申请人： Eric Duchesne ,  Julien Sylvestre

    发明人： Eric Duchesne ,  Julien Sylvestre

    IPC分类号： H01L21/66

    CPC分类号： H01L24/81 ,  H01L22/12 ,  H01L22/20 ,  H01L24/75 ,  H01L2224/131 ,  H01L2224/75272 ,  H01L2224/759 ,  H01L2224/81815 ,  H01L2224/81908 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2224/29099 ,  H01L2224/13099 ,  H01L2924/00

    摘要： Utilizing an appropriately configured laser interferometer, the warpage of a silicon chip can be easily monitored during the solder reflow attachment process in an effort to determine the amount of stress encountered by the chip. Warpage measurements can then be continuously monitored throughout the process and related data can be stored to easily suggest the level of warpage generated by various processing parameters. By dynamically monitoring warpage in conjunction with processing parameters, a correlation can be established between the various parameters chosen, and resulting warpage. Based upon this correlation, the evaluators can easily identify those parameters which produce minimum stress, thus avoiding potential for breakage and damage during reflow operations.

    摘要翻译： 利用适当配置的激光干涉仪，可以在焊料回流附着过程中容易地监测硅芯片的翘曲，以确定芯片遇到的应力的量。 然后可以在整个过程中连续监测翘曲测量，并且可以存储相关数据以容易地建议由各种处理参数产生的翘曲程度。 通过结合处理参数动态监测翘曲，可以在所选择的各种参数之间建立相关性，并产生翘曲。 基于这种相关性，评估者可以容易地识别产生最小应力的那些参数，从而避免在回流操作期间破裂和损坏的可能性。

    Underfill adhesion measurements at a microscopic scale
    5.
    发明授权
    Underfill adhesion measurements at a microscopic scale 有权
    在微观尺度下进行底部填充粘附测量

    公开(公告)号：US08796049B2

    公开(公告)日：2014-08-05

    申请号：US13561661

    申请日：2012-07-30

    申请人： Maxime Cadotte ,  Marie-Claude Paquet ,  Julien Sylvestre

    发明人： Maxime Cadotte ,  Marie-Claude Paquet ,  Julien Sylvestre

    IPC分类号： G01R31/26 ,  H01L21/00 ,  G01N3/24

    CPC分类号： H01L22/12 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00

    摘要： Methods and systems to method to determine an adhesion force of an underfill material to a chip assembled in a flip-chip module are provided. A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate. The method also includes forming a block from the layer of underfill material. The method further includes measuring a force required to shear the block from a surface of the flip-chip module.

    摘要翻译： 提供了用于确定底部填充材料对组装在倒装芯片组件中的芯片的粘附力的方法和系统。 一种方法包括形成倒装芯片模块，其包括连接到具有附着在芯片和基板上的底层填充材料层的基板的芯片。 该方法还包括从底部填充材料层形成块。 该方法还包括测量从倒装芯片模块的表面切割块所需的力。

    Temporary structure to reduce stress and warpage in a flip chip organic package
    9.
    发明授权
    Temporary structure to reduce stress and warpage in a flip chip organic package 失效
    临时结构减少倒装芯片有机封装中的应力和翘曲

    公开(公告)号：US07473618B1

    公开(公告)日：2009-01-06

    申请号：US12107316

    申请日：2008-04-22

    申请人： David Danovitch ,  Julien Sylvestre

    发明人： David Danovitch ,  Julien Sylvestre

    IPC分类号： H01L21/30

    CPC分类号： H01L21/6835 ,  H01L21/50 ,  H01L23/055 ,  H01L23/36 ,  H01L24/81 ,  H01L2221/68318 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/3511 ,  H05K3/3457 ,  H05K2203/016 ,  H05K2203/0271

    摘要： A method for reducing stress and warpage in flip chip packages comprising providing a flip chip package including an organic substrate, an integrated circuit chip, and a cap member, providing a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip, soldering a bottom side of the organic substrate to a top side of the temporary structure, bonding a bottom side of the integrated circuit chip to a top side of the organic substrate with controlled chip collapse columns, coupling the cap member to the top side of the organic substrate, applying force to the flip chip package in a first direction, and applying force to the temporary structure in a second direction opposite the first direction in order to shear the top side of the temporary structure from the bottom side of the organic substrate to remove the temporary structure from the flip chip package.

    摘要翻译： 一种用于减小倒装芯片封装中的应力和翘曲的方法，包括提供包括有机基板，集成电路芯片和盖构件的倒装芯片封装，提供具有基本上类似于 集成电路芯片的热膨胀，将有机基板的底侧焊接到临时结构的顶侧，将集成电路芯片的底侧与受控的芯片倒立柱结合到有机基板的顶侧，将 盖构件到有机基板的顶侧，在第一方向上对倒装芯片封装施加力，并且在与第一方向相反的第二方向上向临时结构施加力，以将临时结构的顶侧剪切 有机基板的底面从倒装芯片封装中去除临时结构。