公开(公告)号：US20100022091A1

公开(公告)日：2010-01-28

申请号：US12180367

申请日：2008-07-25

申请人： SIYI LI ,  Qingjun Zhou ,  Ryan Patz ,  Yifeng Zhou ,  Jeremiah Pender ,  Michael D. Armacost

发明人： SIYI LI ,  Qingjun Zhou ,  Ryan Patz ,  Yifeng Zhou ,  Jeremiah Pender ,  Michael D. Armacost

IPC分类号： H01L21/306

CPC分类号： H01L21/31116 ,  H01J37/3244 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/31138 ,  H01L21/76808 ,  H01L21/76813

摘要： Described herein are methods and apparatuses for etching low-k dielectric layers to form various interconnect structures. In one embodiment, the method includes forming an opening in a resist layer. The method further includes etching a porous low-k dielectric layer with a process gas mixture that includes a fluorocarbon gas and a carbon dioxide (CO2) gas to form vias. The fluorocarbon gas may be C4F6 gas. A ratio of a flow rate of the C4F6 gas to a flow rate of the CO2 gas can vary from approximately 1:2 to 1:10. In another embodiment, the porous low-k dielectric layer is etched with a process gas mixture that includes a fluorocarbon gas and an argon gas with no CHF3 gas to form trenches aligned with the vias in an integrated dual-damascene structure. The fluorocarbon gas may be CF4 gas.

摘要翻译： 这里描述了用于蚀刻低k电介质层以形成各种互连结构的方法和装置。 在一个实施例中，该方法包括在抗蚀剂层中形成开口。 该方法还包括用包括碳氟化合物气体和二氧化碳（CO 2）气体的工艺气体混合物蚀刻多孔低k电介质层以形成通孔。 碳氟化合物气体可以是C 4 F 6气体。 C4F6气体的流量与CO 2气体的流量的比率可以在约1:2至1:10之间变化。 在另一个实施例中，多孔低k电介质层被包括碳氟化合物气体和没有CHF 3气体的氩气的工艺气体混合物进行蚀刻，以形成与整个双镶嵌结构中的通路对准的沟槽。 碳氟化合物气体可以是CF 4气体。

公开(公告)号：US07115534B2

公开(公告)日：2006-10-03

申请号：US10847891

申请日：2004-05-18

申请人： Son Van Nguyen ,  Michael D. Armacost ,  Mehul Naik ,  Girish A. Dixit ,  Ellie Y. Yieh

发明人： Son Van Nguyen ,  Michael D. Armacost ,  Mehul Naik ,  Girish A. Dixit ,  Ellie Y. Yieh

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76808

摘要： Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.

摘要翻译： 提供了用于沉积电介质材料的方法，用作防蚀涂层和牺牲电介质材料在镶嵌形成中。 在一个方面，提供了一种处理衬底的方法，包括通过使含氧有机硅化合物和酸性化合物反应，在酸性电介质层上沉积光致抗蚀剂材料，并使光致抗蚀剂层图形化，在衬底上沉积酸性介电层。 通过蚀刻部分特征定义，沉积酸性电介质材料，蚀刻特征定义的其余部分，然后除去酸性介电材料以形成特征定义，可以将酸性介电层用作形成特征定义的牺牲层。

公开(公告)号：US06829056B1

公开(公告)日：2004-12-07

申请号：US10646943

申请日：2003-08-21

申请人： Michael Barnes ,  John Holland ,  Hongqing Shan ,  Bryan Y. Pu ,  Mohit Jain ,  Zhifeng Sui ,  Michael D. Armacost ,  Neil E. Hanson ,  Diana Xiaobing Ma ,  Ashok K. Sinha ,  Dan Maydan

发明人： Michael Barnes ,  John Holland ,  Hongqing Shan ,  Bryan Y. Pu ,  Mohit Jain ,  Zhifeng Sui ,  Michael D. Armacost ,  Neil E. Hanson ,  Diana Xiaobing Ma ,  Ashok K. Sinha ,  Dan Maydan

IPC分类号： G01B1114

CPC分类号： H01L21/67253 ,  H01J37/32935 ,  H01L21/67069

摘要： A substrate processing apparatus has a chamber having a substrate support, gas distributor, gas energizer, and gas exhaust port. A process monitor is provided to monitor features in a first region of the substrate and generate a corresponding first signal, and to monitor features in a second region of the substrate and generate a second signal. A chamber controller receives and evaluates the first and second signals, and operates the chamber in relation to the signals. For example, the chamber controller can select a process recipe depending upon the signal values. The chamber controller can also set a process parameter at a first level in a first processing sector and at a second level in a second processing sector. The apparatus provides a closed control loop to independently monitor and control processing of features at different regions of the substrate.

摘要翻译： 基板处理装置具有具有基板支撑件，气体分配器，气体激励器和排气口的腔室。 提供过程监视器以​​监测衬底的第一区域中的特征并产生相应的第一信号，并且监测衬底的第二区域中的特征并产生第二信号。 室控制器接收并评估第一和第二信号，并相对于信号操作室。 例如，腔室控​​制器可以根据信号值选择工艺配方。 腔室控制器还可以在第一处理扇区中将处理参数设置在第一电平处，并在第二处理扇区中将第二电平设置为第二电平。 该装置提供一个闭合的控制回路以独立地监测和控制基板的不同区域处的特征的处理。

公开(公告)号：US06750113B2

公开(公告)日：2004-06-15

申请号：US09764832

申请日：2001-01-17

申请人： Michael D. Armacost ,  Andreas K. Augustin ,  Gerald R. Friese ,  John E. Heidenreich, III ,  Gary R. Hueckel ,  Kenneth J. Stein

发明人： Michael D. Armacost ,  Andreas K. Augustin ,  Gerald R. Friese ,  John E. Heidenreich, III ,  Gary R. Hueckel ,  Kenneth J. Stein

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

摘要翻译： 在铜技术中的平行平板电容器形成在其下方没有铜（0.3μm以下）的区域中，底部蚀刻停止层，在TiN层下方具有铝层的复合底板，氧化物电容器电介质和 TiN顶板; 在包括蚀刻顶板以留下电容器区域的过程中，将底板蚀刻到具有在所有侧面上的边缘的较大底部区域; 在电容器顶板的顶表面下沉积具有较高材料质量的层间电介质; 打开接触孔到顶板和底板，并且将互连件下降到两步工艺，其在穿过底板上方的氮化物盖层之后部分地打开下互连和顶板上的氮化物盖层，然后切穿电容器电介质 并完成氮化物盖层的穿透。

公开(公告)号：US08143138B2

公开(公告)日：2012-03-27

申请号：US12240061

申请日：2008-09-29

申请人： Ryan James Patz ,  Igor Peidous ,  Jeremiah Pender ,  Michael D. Armacost

发明人： Ryan James Patz ,  Igor Peidous ,  Jeremiah Pender ,  Michael D. Armacost

IPC分类号： H01L21/76

CPC分类号： H01L21/76807 ,  H01L21/67253 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer.

摘要翻译： 这里描述了制造双镶嵌互连结构的方法。 在一个实施例中，使用具有沟槽然后形成通孔的双镶嵌法制造互连结构。 该方法包括在沟槽和经过蚀刻之后的新型衬垫沉积。 该方法包括蚀刻电介质层中的沟槽。 接下来，该方法包括在介电层上沉积第一衬里层。 接下来，该方法包括蚀刻介电层中的通孔和蚀刻停止层。 接下来，该方法包括在第一衬里层上沉积第二衬里层。 第二衬里层沉积在第一衬里层，电介质层，蚀刻停止层和第一金属层的暴露表面上。 然后，第二金属层沉积在第二衬垫层上。

公开(公告)号：US06656375B1

公开(公告)日：2003-12-02

申请号：US09014806

申请日：1998-01-28

申请人： Michael D. Armacost ,  David M. Dobuzinsky ,  John C. Malinowski ,  Hung Y. Ng ,  Richard S. Wise ,  Chienfan Yu

发明人： Michael D. Armacost ,  David M. Dobuzinsky ,  John C. Malinowski ,  Hung Y. Ng ,  Richard S. Wise ,  Chienfan Yu

IPC分类号： C23F100

CPC分类号： H01L21/31116

摘要： An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.

摘要翻译： 用于衬底的氮化物层的各向异性蚀刻工艺，该方法包括使用包含富氢氟代烃，氧化剂和碳源的蚀刻剂气体。 富氢氟烃优选为CH 3 F或CH 2 F 2之一，碳源优选为CO 2或CO之一，氧化剂优选为O 2。 氟烃优选以约7％-35体积％存在于气体中，氧化剂优选以约1％-35％体积的比例存在于气体中，并且碳源优选以约30％的比例存在于气体中， -92％。

公开(公告)号：US06187412B1

公开(公告)日：2001-02-13

申请号：US08883761

申请日：1997-06-27

申请人： Michael D. Armacost ,  Peter D. Hoh ,  Son V. Nguyen

发明人： Michael D. Armacost ,  Peter D. Hoh ,  Son V. Nguyen

IPC分类号： B32B904

CPC分类号： B01D46/546 ,  B01D67/0072 ,  B01D71/02 ,  B01D71/022 ,  B01D2325/08 ,  B01D2325/26 ,  H01L23/3677 ,  H01L23/3738 ,  H01L2924/0002 ,  Y10T428/12674 ,  Y10T428/12722 ,  Y10T428/24174 ,  Y10T428/24917 ,  H01L2924/00

摘要： A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.

摘要翻译： 一种硅制品，包括硅基和从硅基延伸的列。 列限定了没有材料的柱之间的间隙，使得制品可以用作过滤器或散热器。 还公开了制造硅制品的方法。

公开(公告)号：US5622596A

公开(公告)日：1997-04-22

申请号：US435063

申请日：1995-05-08

申请人： Michael D. Armacost ,  David Dobuzinsky ,  Jeffrey Gambino ,  Son Nguyen

发明人： Michael D. Armacost ,  David Dobuzinsky ,  Jeffrey Gambino ,  Son Nguyen

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/31

CPC分类号： H01L21/31105 ,  Y10S438/97

摘要： Selectivity of SiO.sub.2 to Si.sub.3 N.sub.4 is increased with the additional of silicon rich nitride conformal layer to manufacturing of semiconductor chip. Silicon rich nitride conformal layer may be used in place of or in addition to standard nitride conformal layers in manufacture.

摘要翻译： SiO 2与Si 3 N 4的选择性随着富硅氮化物附加层的附加而增加，从而制造半导体芯片。 富含氮的氮化物保形层可以代替制造中的标准氮化物保形层来代替标准氮化物保形层。

公开(公告)号：US07572734B2

公开(公告)日：2009-08-11

申请号：US11877964

申请日：2007-10-24

申请人： Mehul Naik ,  Suketu A. Parikh ,  Michael D. Armacost

发明人： Mehul Naik ,  Suketu A. Parikh ,  Michael D. Armacost

IPC分类号： H01L21/311

CPC分类号： H01L21/31116 ,  H01J37/32091 ,  H01J37/3266 ,  H01J2237/3347 ,  H01L21/76807 ,  H01L21/76808 ,  H01L22/26

摘要： The etch depth during trench over via etch of a dual damascene structure in a dielectric film stack is controlled to be the same over the dense area and the open area of a substrate and solve micro-loading problems. The trench etch process is adapted to include a forward micro-loading etching process and a reverse micro-loading etching process using two etch chemistries together with the inclusion of a dopant material layer or an organic fill material layer during the deposition of the dielectric film stack. In one embodiment, etching of trenches over vias is switched from forward micro-loading to reverse micro-loading once etching of the dielectric film stack is reached at a predetermined location of a dopant material layer. In another embodiment, etching of an organic trench filling material layer is performed in a reverse micro-loading process followed by etching the dielectric film stack in a forward micro-loading process.

摘要翻译： 电介质膜堆叠中的双镶嵌结构的沟槽过孔蚀刻中的蚀刻深度被控制为在基底的致密区域和开放区域上相同，并且解决微加载问题。 沟槽蚀刻工艺适于包括使用两个蚀刻化学物质的正向微加载蚀刻工艺和反向微加载蚀刻工艺，以及在沉积介电膜堆叠期间包含掺杂剂材料层或有机填充材料层 。 在一个实施例中，一旦在掺杂剂材料层的预定位置处达到电介质膜堆叠的蚀刻，则在通孔上的沟槽的蚀刻从正向微负载切换到反向微负载。 在另一个实施例中，有机沟槽填充材料层的蚀刻在反向微加载过程中进行，然后在正向微加载过程中蚀刻介电膜堆叠。

公开(公告)号：US20080102645A1

公开(公告)日：2008-05-01

申请号：US11555017

申请日：2006-10-31

申请人： Yifeng Zhou ,  Siyi Li ,  Terry Leung ,  Michael D. Armacost

发明人： Yifeng Zhou ,  Siyi Li ,  Terry Leung ,  Michael D. Armacost

IPC分类号： H01L21/3065

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01J37/32706 ,  H01L21/76807

摘要： A substrate comprising a resist layer overlying a dielectric feature, is processed in a substrate processing chamber comprising an antenna, and first and second process electrodes. A process gas comprising CO2 is introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage to the antenna, and by applying to the electrodes, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz. The ratio of the power level of the first bias voltage to the second bias voltage is sufficient to obtain an edge facet height of the underlying dielectric feature that is at least about 10% of the height of the dielectric feature.

摘要翻译： 包括覆盖电介质特征的抗蚀剂层的衬底在包括天线的衬底处理室以及第一和第二处理电极中被处理。 将包含CO 2 2的工艺气体引入室中。 通过向天线施加源电压并且通过向电极施加具有至少约10MHz的第一频率的第一偏置电压和具有第二频率较小的第二偏置电压来对工艺气体进行通电以形成等离子体 大约4 MHz。 第一偏置电压的功率电平与第二偏置电压的比率足以获得至少约为电介质特征高度的约10％的底层电介质特征的边缘面高度。