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    Hidden refresh method and operating method for pseudo SRAM
    1.
    发明授权
    Hidden refresh method and operating method for pseudo SRAM 有权
    伪SRAM的隐藏刷新方法和操作方法

    公开(公告)号：US08576653B2

    公开(公告)日：2013-11-05

    申请号：US13175437

    申请日：2011-07-01

    申请人： Shih-Chin Lin ,  Pei-Geng Ma ,  Yen-Hsueh Huang

    发明人： Shih-Chin Lin ,  Pei-Geng Ma ,  Yen-Hsueh Huang

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40615 ,  G11C2211/4013 ,  G11C2211/4061

    摘要： In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation.

    摘要翻译： 在伪SRAM的示例性隐藏刷新方法中，接收系统时钟。 系统时钟信号的占空比时段适于执行诸如写入或读取操作之类的数据访问操作。 产生经受系统时钟信号控制的刷新时钟信号。 刷新时钟信号的占空比周期与系统时钟信号的占空比周期不重叠。 然后，刷新控制脉冲由刷新时钟信号的占空比周期的起始边沿触发，以激活字线，以执行刷新操作。

    DC/DC converter
    3.
    发明申请
    DC/DC converter 审中-公开
    DC / DC转换器

    公开(公告)号：US20060012357A1

    公开(公告)日：2006-01-19

    申请号：US10892054

    申请日：2004-07-14

    申请人： Shih-Chin Lin ,  Hsiao-Yi Lin ,  Wei Wang

    发明人： Shih-Chin Lin ,  Hsiao-Yi Lin ,  Wei Wang

    IPC分类号： G05F1/40

    CPC分类号： H02M3/073 ,  H02M1/36 ,  H02M2001/0041

    摘要： A DC/DC converter. In the DC/DC converter, a DC/DC conversion circuit provides an output voltage to a storage capacitor upon receiving an enable signal. First and second resistors are connected in series to produce a first voltage according to the output voltage. A Schmitt trigger is coupled to the first voltage to output a first control signal through an inverter when the first voltage is smaller than a second voltage and to output a second control signal through the inverter when the first voltage is higher than a third voltage. An oscillator is turned off upon receiving the first control signal such that the DC/DC conversion circuit stops providing the output voltage, and is turned on and outputs the enable signal upon receiving the second control signal such that the DC/DC conversion circuit provides the output voltage to the storage capacitor.

    摘要翻译： DC / DC转换器。 在DC / DC转换器中，DC / DC转换电路在接收到使能信号时向存储电容器提供输出电压。 第一和第二电阻串联连接以产生根据输出电压的第一电压。 当第一电压小于第二电压时，施密特触发器耦合到第一电压，以通过反相器输出第一控制信号，并且当第一电压高于第三电压时通过反相器输出第二控制信号。 在接收到第一控制信号时，振荡器关闭，使得DC / DC转换电路停止提供输出电压，并且在接收到第二控制信号时导通并输出使能信号，使得DC / DC转换电路提供 输出电压到存储电容。

    Low leakage current static random access memory
    4.
    发明授权
    Low leakage current static random access memory 失效
    低泄漏电流静态随机存取存储器

    公开(公告)号：US06970374B2

    公开(公告)日：2005-11-29

    申请号：US10708328

    申请日：2004-02-24

    申请人： Shih-Chin Lin

    发明人： Shih-Chin Lin

    IPC分类号： G11C11/00 ,  G11C11/412

    CPC分类号： G11C11/412

    摘要： A static random access memory (SRAM) has a plurality of SRAM cells, a first switch unit, a second switch unit, and a capacitor. During read/write operations of the SRAM cells, the first switch unit and the second switch unit are turned on so that two power terminals of the SRAM cells respectively electrically connect to VDD and VSS and that the capacitor electrically connects between VDD and VSS. When the SRAM cells are not accessed, the first switch unit and the second switch unit are turned off and the capacitor keeps a voltage gap between the two power terminals of the SRAM cells greater than a predetermined value.

    摘要翻译： 静态随机存取存储器（SRAM）具有多个SRAM单元，第一开关单元，第二开关单元和电容器。 在SRAM单元的读/写操作期间，第一开关单元和第二开关单元导通，使得SRAM单元的两个电源端子分别电连接到V DD和V SS 并且电容器在V DD和V SS之间电连接。 当SRAM单元未被访问时，第一开关单元和第二开关单元断开，并且电容器保持SRAM单元的两个电源端子之间的电压间隙大于预定值。

    APPARATUS AND METHOD FOR IMAGE CORRECTION
    5.
    发明申请
    APPARATUS AND METHOD FOR IMAGE CORRECTION 审中-公开
    用于图像校正的装置和方法

    公开(公告)号：US20120106868A1

    公开(公告)日：2012-05-03

    申请号：US13286300

    申请日：2011-11-01

    申请人： Shih-Chin Lin

    发明人： Shih-Chin Lin

    IPC分类号： G06K9/40

    CPC分类号： G06T11/001 ,  G06T7/38

    摘要： An image correction apparatus for correcting an original image captured by a photographing device is provided. The image correction apparatus includes a storage and a texture mapping module. The storage therein stores mapping data sets associated with the photographing device. The invention is able to construct and utilize mapping data associated with a particular optical lens when used as part of the photographic device. The texture mapping module corrects an original captured image using a texture mapping procedure according to the appropriate mapping data to generate a corrected image. The texture mapping procedure may use mapping data in a polygon based approach to generate corrected images more efficiently.

    摘要翻译： 提供了一种用于校正由拍摄装置拍摄的原始图像的图像校正装置。 图像校正装置包括存储和纹理映射模块。 其中的存储存储与拍摄装置相关联的映射数据集。 当用作照相设备的一部分时，本发明能够构建和利用与特定光学透镜相关联的映射数据。 纹理映射模块使用根据适当的映射数据的纹理映射过程校正原始捕获的图像，以生成校正图像。 纹理映射过程可以使用基于多边形的方法中的映射数据来更有效地生成校正图像。

    Shift register and shift register set using the same
    6.
    发明授权
    Shift register and shift register set using the same 有权
    移位寄存器和移位寄存器组使用相同

    公开(公告)号：US07499517B2

    公开(公告)日：2009-03-03

    申请号：US11035784

    申请日：2005-01-13

    申请人： Shih-Chin Lin ,  Hsiao-Yi Lin

    发明人： Shih-Chin Lin ,  Hsiao-Yi Lin

    IPC分类号： G11C19/00

    CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/28 ,  G11C19/287

    摘要： A shift register and a shift register are provided. The shift register comprises the switch circuit, the latch circuit, and the inverter circuit 170. The shift register set, by alternately-serially connecting two types of shift registers, can receive two clock signals and an initial pulse signal to control the output waveform. The output of the present stage shift register can be used to control the turn-on time of the nest stage shift register. Further, by changing the circuit driving signal from the dynamic signal to the static signal, the circuit can operate only when the signal is “0” or “1” without being affected by the signal rising time and the falling time so that the circuit can operate in a more stable status.

    摘要翻译： 提供了移位寄存器和移位寄存器。 移位寄存器包括开关电路，锁存电路和逆变器电路170.通过交替串联连接两种类型的移位寄存器的移位寄存器可以接收两个时钟信号和初始脉冲信号来控制输出波形。 当前级移位寄存器的输出可用于控制嵌套级移位寄存器的导通时间。 此外，通过将电路驱动信号从动态信号改变为静态信号，电路仅在信号为“0”或“1”时才能工作，而不受信号上升时间和下降时间的影响，使得电路可以 经营状况更加稳定。

    Shift register and shift register set using the same
    7.
    发明申请
    Shift register and shift register set using the same 有权
    移位寄存器和移位寄存器组使用相同

    公开(公告)号：US20050289422A1

    公开(公告)日：2005-12-29

    申请号：US11035784

    申请日：2005-01-13

    申请人： Shih-Chin Lin ,  Hsiao-Yi Lin

    发明人： Shih-Chin Lin ,  Hsiao-Yi Lin

    IPC分类号： G01R31/28 ,  G11C19/38

    CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0286 ,  G11C19/00 ,  G11C19/28 ,  G11C19/287

    摘要： A shift register and a shift register are provided. The shift register comprises the switch circuit, the latch circuit, and the inverter circuit 170. The shift register set, by alternately-serially connecting two types of shift registers, can receive two clock signals and an initial pulse signal to control the output waveform. The output of the present stage shift register can be used to control the turn-on time of the nest stage shift register. Further, by changing the circuit driving signal from the dynamic signal to the static signal, the circuit can operate only when the signal is “0” or “1” without being affected by the signal rising time and the falling time so that the circuit can operate in a more stable status.

    摘要翻译： 提供了移位寄存器和移位寄存器。 移位寄存器包括开关电路，锁存电路和逆变器电路170.通过交替串联连接两种类型的移位寄存器的移位寄存器可以接收两个时钟信号和初始脉冲信号来控制输出波形。 当前级移位寄存器的输出可用于控制嵌套级移位寄存器的导通时间。 此外，通过将电路驱动信号从动态信号改变为静态信号，电路仅在信号为“0”或“1”时才能工作，而不受信号上升时间和下降时间的影响，使得电路可以 经营状况更加稳定。

    Method for burn-in operation on a wafer of memory devices
    8.
    发明授权
    Method for burn-in operation on a wafer of memory devices 失效
    用于存储器件晶片上的老化操作的方法

    公开(公告)号：US5946248A

    公开(公告)日：1999-08-31

    申请号：US32401

    申请日：1998-02-27

    申请人： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

    发明人： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

    IPC分类号： G01R31/28 ,  G11C29/50 ,  G11C13/00

    CPC分类号： G11C29/50 ,  G01R31/2856 ,  G11C11/401

    摘要： A method is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this method, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

    摘要翻译： 提供一种在形成有多个骰子的晶片上使用的方法，每个骰子上具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过这种方法，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。

    HIDDEN REFRESH METHOD AND OPERATING METHOD FOR PSEUDO SRAM
    10.
    发明申请
    HIDDEN REFRESH METHOD AND OPERATING METHOD FOR PSEUDO SRAM 有权
    用于PSEUDO SRAM的隐藏刷新方法和操作方法

    公开(公告)号：US20130003481A1

    公开(公告)日：2013-01-03

    申请号：US13175437

    申请日：2011-07-01

    申请人： Shih-Chin LIN ,  Pei-Geng Ma ,  Yen-Hsueh Huang

    发明人： Shih-Chin LIN ,  Pei-Geng Ma ,  Yen-Hsueh Huang

    IPC分类号： G11C11/402

    CPC分类号： G11C11/40615 ,  G11C2211/4013 ,  G11C2211/4061

    摘要： In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation.

    摘要翻译： 在伪SRAM的示例性隐藏刷新方法中，接收系统时钟。 系统时钟信号的占空比时段适于执行诸如写入或读取操作之类的数据访问操作。 产生经受系统时钟信号控制的刷新时钟信号。 刷新时钟信号的占空比周期与系统时钟信号的占空比周期不重叠。 然后，刷新控制脉冲由刷新时钟信号的占空比周期的起始边沿触发，以激活字线，以执行刷新操作。