公开(公告)号：US09165848B2

公开(公告)日：2015-10-20

申请号：US14347505

申请日：2011-09-29

Applicant: Hirotaka Ohno ,  Takuya Kadoguchi

Inventor： Hirotaka Ohno ,  Takuya Kadoguchi

IPC: H01L23/10 ,  H01L23/48 ,  H01L23/28 ,  H01L25/18 ,  H01L23/433 ,  H01L23/492 ,  H01L25/07 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/28 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/562 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/3754 ,  H01L2224/40137 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: This semiconductor device includes: a first metal plate; a plurality of semiconductor elements mounted on the first metal plate; a spacer that is connected to a surface on the opposite side to the surface where the plurality of semiconductor elements are mounted on the first metal plate; a second metal plate that is connected to a surface on the opposite side to the surface where the spacer is connected to the semiconductor elements; and an encapsulating resin between the first plate and the second plate that seals the plurality of semiconductor elements. Stress due to contraction that occurs in the encapsulating resin between the plurality of semiconductor elements is relaxed to a greater extent than stress due to contraction that occurs in the encapsulating resin in the locations other than the location between the plurality of semiconductor devices.

Abstract translation: 该半导体装置包括：第一金属板; 安装在所述第一金属板上的多个半导体元件; 连接到与所述多个半导体元件安装在所述第一金属板上的表面相反侧的表面的间隔件; 第二金属板，其连接到与间隔件连接到半导体元件的表面相反侧的表面; 以及密封所述多个半导体元件的所述第一板和所述第二板之间的封装树脂。 由于在多个半导体元件之间的位置以外的位置处发生在封装树脂中的收缩引起的由于在多个半导体元件之间的封装树脂中发生的收缩而产生的收缩的应力被更大程度地松弛。

公开(公告)号：US20070284735A1

公开(公告)日：2007-12-13

申请号：US11596755

申请日：2005-10-06

Applicant: Kazumasa Tanida ,  Shigo Higuchi ,  Takuya Kadoguchi

Inventor： Kazumasa Tanida ,  Shigo Higuchi ,  Takuya Kadoguchi

IPC: H01L23/12

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device (1, 1A, 21, 31, 41, 51) provided with a first semiconductor chip (3) having a first functional surface (3F) formed with a first functional element (3a), a protective resin layer (12) provided on the first functional surface, and an external connection terminal (10, 19, 52) provided on a peripheral portion of the first functional surface for external electrical connection, the external connection terminal having a bottom surface (10B, 19BB) exposed from a bottom surface (12B) of the protective resin layer facing away from the first functional surface and a side surface (10S, 19BS) exposed from a side surface (12S) of the protective resin layer.

Abstract translation: 设置有具有形成有第一功能元件（3a）的第一功能面（3F）的第一半导体芯片（3）的半导体装置（1,1A，21,41,41），保护树脂层 （12），设置在所述第一功能面的外部电连接的周边部的外部连接端子（10,19,52），所述外部连接端子具有底面（10B，19 BB）从保护树脂层的背离第一功能表面的底表面（12A）暴露的侧表面（10A，BBS）以及从保护树脂层的侧表面（12S）露出的侧表面（10S，19BS）。

公开(公告)号：US20150028464A1

公开(公告)日：2015-01-29

申请号：US14314485

申请日：2014-06-25

Applicant: Takuya KADOGUCHI ,  Takahiro HIRANO ,  Arata HARADA ,  Masayoshi NISHIHATA ,  Tomomi OKUMURA

Inventor： Takuya KADOGUCHI ,  Takahiro HIRANO ,  Arata HARADA ,  Masayoshi NISHIHATA ,  Tomomi OKUMURA

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/85 ,  H01L24/89 ,  H01L2224/48247 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to the disclosure, a lead frame is provided, which includes: a first island and a second island that are arranged side by side; an outer peripheral frame; first leads that extend in a second direction perpendicular to the first direction; second leads that extend in the second direction; a first coupling portion that couples the first leads to the frame; a second coupling portion that couples the second leads to the frame; an intermediate portion formed between the first and second coupling portions in the first direction such that it extends in the second direction to terminate before the space between the first and second islands; and a deformation restraining portion formed or provided in at least one of the first leads, the second leads, the first and the second coupling portions and configured to restrain deformations of the first and second leads during a molding process.

Abstract translation: 根据本发明，提供一种引线框，其包括：并排布置的第一岛和第二岛; 外围框架; 在垂直于第一方向的第二方向上延伸的第一引线; 在第二方向延伸的第二引线; 第一耦合部分，其将第一引线耦合到框架; 第二耦合部分，其将所述第二引线耦合到所述框架; 在第一方向上形成在第一和第二联接部分之间的中间部分，使得其在第二方向上延伸以在第一和第二岛之间的空间之前终止; 以及形成或设置在所述第一引线，所述第二引线，所述第一和第二联接部中的至少一个中并且被构造成在模制处理期间抑制所述第一引线和所述第二引线的变形的变形抑制部。

公开(公告)号：US20140197525A1

公开(公告)日：2014-07-17

申请号：US14117165

申请日：2011-05-16

Applicant: Takuya Kadoguchi ,  Yoshikazu Suzuki ,  Masaya Kaji ,  Takanori Kawashima

Inventor： Takuya Kadoguchi ,  Yoshikazu Suzuki ,  Masaya Kaji ,  Takanori Kawashima

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/492 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/33 ,  H01L24/45 ,  H01L25/18 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4917 ,  H01L2224/73265 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A power module configured to arrange a first electrode on a surface of which a first switching device is bonded, a second electrode on a surface of which a second switching device is bonded, and a third electrode by stacking the first electrode, the first switching device, the second electrode, the second switching device, and the third electrode in this order from the bottom in a stacking direction, characterized by first through third electrode pieces each connected to the first through third electrodes, first and second signal lines each connected to the first and second switching devices, wherein the first through third electrode pieces and the first and second signal lines are provided extending outward in the same plane as the second electrode.

Abstract translation: 一种电源模块，被配置为在其表面上结合有第一开关装置的第一电极，在其表面上接合第二开关装置的第二电极和通过堆叠所述第一电极的第三电极，所述第一开关装置 ，第二电极，第二开关器件和第三电极，从堆叠方向的底部开始，其特征在于，第一至第三电极片分别连接到第一至第三电极，第一和第二信号线各自连接到 第一和第二开关器件，其中第一至第三电极片以及第一和第二信号线设置在与第二电极相同的平面内向外延伸。

公开(公告)号：US20140159230A1

公开(公告)日：2014-06-12

申请号：US14096172

申请日：2013-12-04

Applicant: Takuya KADOGUCHI

Inventor： Takuya KADOGUCHI

IPC: H01L23/00

CPC classification number: H01L23/051 ,  H01L23/3107 ,  H01L23/36 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor element in the form of a flat plate that has opposed first and second surfaces, an insulating layer that covers control wiring located on the first surface side of the semiconductor element, a metal block that is bonded to the first surface side of the semiconductor element via a solder layer, and a protective film that is formed between the metal block and the insulating layer, the protective film having a hardness equal to or greater than a hardness of the metal block. When viewed from the first surface side, the protective film is formed in an area at least including a position where an edge portion of the metal block and the control wiring cross each other.

Abstract translation: 半导体器件包括具有相对的第一和第二表面的平板形式的半导体元件，覆盖位于半导体元件的第一表面侧上的控制布线的绝缘层，接合到第一表面的金属块 以及形成在金属块和绝缘层之间的保护膜，所述保护膜的硬度等于或大于所述金属块的硬度。 当从第一表面侧观察时，保护膜形成在至少包括金属块的边缘部分和控制配线彼此交叉的位置的区域中。

公开(公告)号：US08742556B2

公开(公告)日：2014-06-03

申请号：US13349993

申请日：2012-01-13

Applicant: Takuya Kadoguchi ,  Tomomi Okumura ,  Tatsuya Miyoshi

Inventor： Takuya Kadoguchi ,  Tomomi Okumura ,  Tatsuya Miyoshi

IPC: H01L23/495

CPC classification number: H01L23/4334 ,  H01L23/3142 ,  H01L23/473 ,  H01L23/492 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/06181 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3656 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor module comprises: a metal block; a semiconductor device installed via a solder layer in a semiconductor device installation area on a surface of the metal block; and a molded portion formed by molding a resin on the metal block and the semiconductor device; wherein the surface of the metal block includes a plating area and a roughened area, and the semiconductor device installation area is provided in the plating area.

Abstract translation: 半导体模块包括：金属块; 半导体器件，其通过焊料层安装在所述金属块的表面上的半导体器件安装区域中; 以及通过在所述金属块和所述半导体器件上模制树脂而形成的模制部分; 其中金属块的表面包括电镀区域和粗糙区域，并且半导体器件安装区域设置在电镀区域中。

公开(公告)号：US20120181679A1

公开(公告)日：2012-07-19

申请号：US13349993

申请日：2012-01-13

Applicant: Takuya KADOGUCHI ,  Tomomi OKUMURA ,  Tatsuya MIYOSHI

Inventor： Takuya KADOGUCHI ,  Tomomi OKUMURA ,  Tatsuya MIYOSHI

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L23/4334 ,  H01L23/3142 ,  H01L23/473 ,  H01L23/492 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/06181 ,  H01L2224/27013 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3656 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor module comprises: a metal block; a semiconductor device installed via a solder layer in a semiconductor device installation area on a surface of the metal block; and a molded portion formed by molding a resin on the metal block and the semiconductor device; wherein the surface of the metal block includes a plating area and a roughened area, and the semiconductor device installation area is provided in the plating area.

Abstract translation: 半导体模块包括：金属块; 半导体器件，其通过焊料层安装在所述金属块的表面上的半导体器件安装区域中; 以及通过在所述金属块和所述半导体器件上模制树脂而形成的模制部分; 其中金属块的表面包括电镀区域和粗糙区域，并且半导体器件安装区域设置在电镀区域中。

公开(公告)号：US08884411B2

公开(公告)日：2014-11-11

申请号：US14112408

申请日：2012-04-18

Applicant: Takuya Kadoguchi ,  Shingo Iwasaki ,  Takanori Kawashima ,  Tomomi Okumura ,  Masayoshi Nishihata

Inventor： Takuya Kadoguchi ,  Shingo Iwasaki ,  Takanori Kawashima ,  Tomomi Okumura ,  Masayoshi Nishihata

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L24/30 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/84205 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device includes a first semiconductor element; a first thick plate portion that is electrically connected to an electrode on a lower surface side of the first semiconductor element, and is formed by a conductor; a second semiconductor element that is arranged such that a main surface of the second semiconductor element faces a main surface of the first semiconductor element; a second thick plate portion that is electrically connected to an electrode on a lower surface side of the second semiconductor element, and is formed by a conductor; a third thick plate portion that is electrically connected to an electrode on an upper surface side of the first semiconductor element, and is formed by a conductor; a fourth thick plate portion that is electrically connected to an electrode on an upper surface side of the second semiconductor element, and is formed by a conductor; a first thin plate portion that is provided on the second thick plate portion, is formed by a conductor, and is thinner than the second thick plate portion; and a second thin plate portion that is provided on the third thick plate portion, is formed by a conductor, and is thinner than the third thick plate portion. The first thin plate portion and the second thin plate portion are fixed together and electrically connected.

Abstract translation: 半导体器件包括第一半导体元件; 与第一半导体元件的下表面侧的电极电连接并由导体形成的第一厚板部; 第二半导体元件，被布置成使得第二半导体元件的主表面面对第一半导体元件的主表面; 第二厚板部分，电连接到第二半导体元件的下表面侧的电极，并由导体形成; 第三厚板部，与第一半导体元件的上表面侧的电极电连接，由导体形成; 与第二半导体元件的上表面侧的电极电连接并由导体形成的第四厚板部; 设置在第二厚板部分上的第一薄板部分由导体形成，并且比第二厚板部分薄; 并且设置在第三厚板部分上的第二薄板部分由导体形成，并且比第三厚板部分薄。 第一薄板部分和第二薄板部分固定在一起并电连接。

公开(公告)号：US20140264819A1

公开(公告)日：2014-09-18

申请号：US14206781

申请日：2014-03-12

Applicant: Tomomi Okumura ,  Takuya Kadoguchi

Inventor： Tomomi Okumura ,  Takuya Kadoguchi

IPC: H01L23/367

CPC classification number: H01L23/3672 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/49562 ,  H01L2224/49175 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a link portion that connects a second heat sink to a third heat sink via a solder. The solder is arranged on a connecting surface of a base portion of the link portion, which is orthogonal to a plate thickness direction of the base portion, in a direction perpendicular to first and second surfaces. The link portion has a rib that protrudes from the base portion in a direction orthogonal to the first and second surfaces, and a thickness of a portion where the rib is provided is equal to or less than the thickness of the corresponding heat sink. The rib is provided across an entire length of a first region that is sealed by a sealing resin body and that is between the second and the third heat sinks, in an alignment direction of a first heat sink and the third heat sink.

Abstract translation: 半导体器件包括通过焊料将第二散热器连接到第三散热器的连接部分。 焊料沿与第一表面和第二表面垂直的方向布置在与基部的板厚度方向正交的连接部的基部的连接表面上。 连杆部分具有在与第一和第二表面正交的方向上从基部突出的肋，并且肋的设置部分的厚度等于或小于相应的散热器的厚度。 在第一散热器和第三散热器的排列方向上，肋被设置在由密封树脂体密封并且位于第二和第三散热器之间的第一区域的整个长度上。

公开(公告)号：US20140232016A1

公开(公告)日：2014-08-21

申请号：US14347505

申请日：2011-09-29

Applicant: Hirotaka Ohno ,  Takuya Kadoguchi

Inventor： Hirotaka Ohno ,  Takuya Kadoguchi

IPC: H01L23/28

CPC classification number: H01L23/28 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/492 ,  H01L23/562 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/3754 ,  H01L2224/40137 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: This semiconductor device includes: a first metal plate; a plurality of semiconductor elements mounted on the first metal plate; a spacer that is connected to a surface on the opposite side to the surface where the plurality of semiconductor elements are mounted on the first metal plate; a second metal plate that is connected to a surface on the opposite side to the surface where the spacer is connected to the semiconductor elements; and an encapsulating resin between the first plate and the second plate that seals the plurality of semiconductor elements. Stress due to contraction that occurs in the encapsulating resin between the plurality of semiconductor elements is relaxed to a greater extent than stress due to contraction that occurs in the encapsulating resin in the locations other than the location between the plurality of semiconductor devices.

Abstract translation: 该半导体装置包括：第一金属板; 安装在所述第一金属板上的多个半导体元件; 连接到与所述多个半导体元件安装在所述第一金属板上的表面相反侧的表面的间隔件; 第二金属板，其连接到与间隔件连接到半导体元件的表面相反侧的表面; 以及密封所述多个半导体元件的所述第一板和所述第二板之间的封装树脂。 由于在多个半导体元件之间的位置以外的位置处发生在封装树脂中的收缩引起的由于在多个半导体元件之间的封装树脂中发生的收缩而产生的收缩的应力被更大程度地松弛。