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公开(公告)号：US09368437B2
公开(公告)日：2016-06-14
申请号：US13977658
申请日：2011-12-31
IPC分类号： H01L23/498 , H01L23/00 , H01L21/768 , H01L23/50 , H01L23/538
CPC分类号： H01L23/49811 , H01L21/76885 , H01L23/50 , H01L23/5386 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/11849 , H01L2224/1301 , H01L2224/13013 , H01L2224/13014 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/13687 , H01L2224/14132 , H01L2224/14133 , H01L2224/14135 , H01L2224/14136 , H01L2224/16013 , H01L2224/16014 , H01L2224/16058 , H01L2224/16238 , H01L2224/1703 , H01L2224/17051 , H01L2224/81191 , H01L2224/81203 , H01L2224/81385 , H01L2224/81395 , H01L2224/81411 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H01L2924/05042 , H01L2924/1434 , H01L2924/381 , H01L2924/3841 , H01L2924/014 , H01L2924/00014
摘要： Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
摘要翻译： 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。
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公开(公告)号：US20140217579A1
公开(公告)日：2014-08-07
申请号：US13977658
申请日：2011-12-31
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/49811 , H01L21/76885 , H01L23/50 , H01L23/5386 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11831 , H01L2224/11849 , H01L2224/1301 , H01L2224/13013 , H01L2224/13014 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13562 , H01L2224/1357 , H01L2224/13687 , H01L2224/14132 , H01L2224/14133 , H01L2224/14135 , H01L2224/14136 , H01L2224/16013 , H01L2224/16014 , H01L2224/16058 , H01L2224/16238 , H01L2224/1703 , H01L2224/17051 , H01L2224/81191 , H01L2224/81203 , H01L2224/81385 , H01L2224/81395 , H01L2224/81411 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H01L2924/05042 , H01L2924/1434 , H01L2924/381 , H01L2924/3841 , H01L2924/014 , H01L2924/00014
摘要： Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
摘要翻译： 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。
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3.发明申请公开(公告)号：US20200098727A1
公开(公告)日：2020-03-26
申请号：US16141415
申请日：2018-09-25
申请人： Debendra Mallik , Robert L. Sankman , Sanka Ganesan , George Vakanas , Omkar Karhade , Sri Chaitra Jyotsna Chavali , Zhaozhi George Li , Holly A. Sawyer
发明人： Debendra Mallik , Robert L. Sankman , Sanka Ganesan , George Vakanas , Omkar Karhade , Sri Chaitra Jyotsna Chavali , Zhaozhi George Li , Holly A. Sawyer
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00 , H01L23/538
摘要： A wire-bond memory die is coupled to a system-on-chip processor where the processor is flip-chip mounted on a semiconductor package substrate, and the wire-bond memory die is also flip-chip configured through a redistribution layer that pins out to a series of pillars that contact the semiconductor package substrate. The wire-bond memory die is stacked on the processor and the redistribution layer overhangs the processor to contact the series of pillars.
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公开(公告)号：US20180005928A1
公开(公告)日：2018-01-04
申请号：US15198107
申请日：2016-06-30
申请人： Robert L. Sankman , Sanka Ganesan
发明人： Robert L. Sankman , Sanka Ganesan
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , H01L21/56
CPC分类号： H01L23/49811 , H01L21/4853 , H01L21/565 , H01L23/3114 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/08238 , H01L2224/131 , H01L2224/13294 , H01L2224/133 , H01L2224/16237 , H01L2224/16238 , H01L2224/81191 , H01L2224/81192 , H01L2224/81401 , H01L2224/81411 , H01L2224/81416 , H01L2224/81438 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81473 , H01L2224/81815 , H01L2924/01004 , H01L2924/01028 , H01L2924/01029 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/1532 , H01L2924/15747 , H01L2924/00014 , H01L2924/014
摘要： Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.
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公开(公告)号：US09420693B2
公开(公告)日：2016-08-16
申请号：US14490615
申请日：2014-09-18
IPC分类号： H05K1/00 , H05K1/18 , H01L21/48 , H01L23/498 , H05K1/09 , H05K1/11 , H05K3/00 , H05K3/18 , H05K3/46
CPC分类号： H01G4/33 , H01L21/4857 , H01L23/49822 , H01L23/49827 , H01L2224/16225 , H01L2924/15311 , H05K1/09 , H05K1/115 , H05K1/162 , H05K1/185 , H05K3/0017 , H05K3/188 , H05K3/4644 , H05K3/467 , H05K2201/10015
摘要： An embedded thin film capacitor and methods of its fabrication are disclosed. The embedded thin film capacitor includes two conductive plates separated by a dielectric layer. In embodiments, the capacitor is enclosed within a package substrate. A method of forming the embedded thin film capacitor includes forming a first insulating layer on a bottom plate and a first trace. A first opening is then formed in a first insulating layer to expose a first region of a bottom plate. An adhesive layer is then formed on the first insulating layer and on top of the exposed first region of the bottom plate. A second opening is formed through the insulating layer and the first insulating layer to expose a second region of the bottom plate. A top plate is formed within the first opening and a via is formed within the second opening.
摘要翻译： 公开了一种嵌入式薄膜电容器及其制造方法。 嵌入式薄膜电容器包括由电介质层分开的两个导电板。 在实施例中，电容器封装在封装衬底内。 形成嵌入式薄膜电容器的方法包括在底板和第一迹线上形成第一绝缘层。 然后在第一绝缘层中形成第一开口以暴露底板的第一区域。 然后在第一绝缘层上和在底板的暴露的第一区域的顶部上形成粘合剂层。 通过绝缘层和第一绝缘层形成第二开口以露出底板的第二区域。 顶板形成在第一开口内，并在第二开口内形成通孔。
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6.发明授权Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages 有权封装的半导体芯片，具有无冲击积层（BBUL）封装的无冲击模封装接口公开(公告)号：US09224674B2
公开(公告)日：2015-12-29
申请号：US13996495
申请日：2011-12-15
IPC分类号： H01L27/08 , H01L23/552 , H01L23/48 , H01L23/00
CPC分类号： H01L24/09 , H01L23/481 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L24/19 , H01L24/97 , H01L27/08 , H01L2224/04105 , H01L2224/08235 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/15153 , H01L2924/00 , H01L2224/83 , H01L2224/82
摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.
摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。
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7.发明授权公开(公告)号：US09099444B2
公开(公告)日：2015-08-04
申请号：US13995778
申请日：2011-12-22
申请人： Debendra Mallik , Robert L. Sankman
发明人： Debendra Mallik , Robert L. Sankman
CPC分类号： H01L25/0657 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/82 , H01L23/3114 , H01L23/3135 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/051 , H01L2224/05147 , H01L2224/05541 , H01L2224/05571 , H01L2224/056 , H01L2224/05647 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/141 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16265 , H01L2224/1703 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81986 , H01L2224/9202 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06568 , H01L2225/06582 , H01L2924/00014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/14335 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1461 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2224/81 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/05552 , H01L2924/01079 , H01L2224/11
摘要： 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
摘要翻译： 描述了具有通过模具一级互连的3D集成电路封装以及形成这种封装的方法。 例如，半导体封装包括衬底。 底部半导体管芯具有表面积的活性侧。 底部半导体管芯与主体侧远离衬底耦合到衬底。 顶部半导体管芯具有活性侧，其表面积大于底部半导体管芯的表面积。 顶部半导体管芯耦合到衬底，其中有源侧靠近衬底。 底部半导体管芯的有源侧面向并导电耦合到顶部半导体管芯的有源侧。 顶部半导体管芯通过旁路底部半导体管芯的一级互连导体耦合到衬底。
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公开(公告)号：US20140171751A1
公开(公告)日：2014-06-19
申请号：US13719360
申请日：2012-12-19
IPC分类号： A61B5/0205 , A61B5/024 , A61B5/145 , A61B5/021 , A61B5/0488 , A61N5/00 , A61B5/01 , A61B5/0245 , A61N1/36 , A61N5/06 , A61H99/00 , A61B5/00 , A61B5/0476
CPC分类号： A61B5/02055 , A61B5/0002 , A61B5/0004 , A61B5/0006 , A61B5/0008 , A61B5/0205 , A61B5/021 , A61B5/02438 , A61B5/0245 , A61B5/0476 , A61B5/0488 , A61B5/14532 , A61B5/14542 , A61B5/4839 , A61B5/681 , A61H23/02 , A61H2201/501 , A61H2201/5097 , A61H2230/06 , A61H2230/10 , A61H2230/202 , A61H2230/30 , A61H2230/50 , A61H2230/60 , A61N1/36003 , A61N1/37229 , A61N1/37282
摘要： Described herein are technologies related to a wireless electronic vital sign monitoring of a person. More particularly, detecting vital signs and processing of the detected vital signs using a bio monitoring patch.
摘要翻译： 这里描述了与人的无线电子生命体征监测有关的技术。 更具体地，使用生物监测补片检测生命体征并检测检测到的生命体征。
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公开(公告)号：US20120077357A1
公开(公告)日：2012-03-29
申请号：US12890646
申请日：2010-09-25
申请人： Bin Zou , Yan Guo , Robert L. Sankman , Jiangqi He
发明人： Bin Zou , Yan Guo , Robert L. Sankman , Jiangqi He
CPC分类号： H01R43/16 , H01L23/49811 , H01L2924/0002 , H01R12/57 , H01R2103/00 , H05K1/0219 , H05K1/0231 , H05K1/0242 , H05K1/0251 , H05K1/113 , H05K2201/09336 , H05K2201/09663 , H05K2201/1031 , Y02P70/611 , Y10T29/49204 , H01L2924/00
摘要： Methods and apparatus relating to self-referencing pins are described. In one embodiment, a pin electrically couples a first agent to a second agent. The pin includes two or more portions that are at least partially separated by an insulator, e.g., to improve crosstalk performance. Other embodiments are also disclosed and claimed.
摘要翻译： 描述与自引用引脚相关的方法和装置。 在一个实施例中，引脚将第一试剂电耦合到第二试剂。 该销包括至少部分地被绝缘体隔开的两个或多个部分，例如，以提高串扰性能。 还公开并要求保护其他实施例。
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公开(公告)号：US07133294B2
公开(公告)日：2006-11-07
申请号：US11080126
申请日：2005-03-15
申请人： Priyavadan R. Patel , Chee-Yee Chung , David G. Figueroa , Robert L. Sankman , Yuan-Liang Li , Hong Xie , William P. Pinello
发明人： Priyavadan R. Patel , Chee-Yee Chung , David G. Figueroa , Robert L. Sankman , Yuan-Liang Li , Hong Xie , William P. Pinello
CPC分类号： H01L24/81 , H01L23/50 , H01L2224/16225 , H01L2224/16265 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.
摘要翻译： 为了提供高速，低电感电容去耦，集成电路（IC）封装包括位于管芯和IC封装衬底之间的安装区域内的电容器。 各种类型和尺寸的电容器和基板可以用于各种几何布置。 在一些实施例中，电容器夹在裸片端子或凸起之间以及衬底导体或衬垫之间，而在其它实施例中，电容器位于IC封装衬底的表面上的棒状导体之间。 还描述了制造方法以及将包装应用于电子组件和电子系统。
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