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    METHOD OF PACKAGING SEMICONDUCTOR DIE
    2.
    发明申请
    METHOD OF PACKAGING SEMICONDUCTOR DIE 有权
    包装半导体器件的方法

    公开(公告)号：US20130113091A1

    公开(公告)日：2013-05-09

    申请号：US13292103

    申请日：2011-11-09

    申请人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V.C. Muniandy ,  Weng Foong Yap

    发明人： Dominic Koey Poh Meng ,  Zhiwei Gong ,  Kesvakumar V.C. Muniandy ,  Weng Foong Yap

    IPC分类号： H01L23/28 ,  B29C33/12 ,  H01L21/56

    CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L21/568 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

    摘要： A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.

    摘要翻译： 封装半导体管芯的方法包括使用嵌入式接地层或嵌入式嵌入式单元。 嵌入式单元是具有至少一个空腔的单个独立单元。 嵌入式单元被放置在过程安装表面的封装区域内和之内。 嵌入式单元可以具有不同的尺寸和形状以及在处理半导体管芯期间可以放置在基板，面板或带上的预定位置中的多个不同的空腔，该半导体管芯嵌入到再分布芯片封装（RCP）或晶片级封装 WFL）面板。 嵌入式单元提供功能和设计灵活性，可以在单个处理面板或批次中运行多个嵌入式单元和半导体管芯或具有不同尺寸和尺寸的部件，并减少封装和封装后固化期间的裸片漂移，移动或偏斜。

    DEVICES AND STACKED MICROELECTRONIC PACKAGES WITH PARALLEL CONDUCTORS AND INTRA-CONDUCTOR ISOLATOR STRUCTURES AND METHODS OF THEIR FABRICATION
    8.
    发明申请
    DEVICES AND STACKED MICROELECTRONIC PACKAGES WITH PARALLEL CONDUCTORS AND INTRA-CONDUCTOR ISOLATOR STRUCTURES AND METHODS OF THEIR FABRICATION 有权
    具有并联导体和导体导体隔离器结构的器件和堆叠微电子封装及其制造方法

    公开(公告)号：US20150092372A1

    公开(公告)日：2015-04-02

    申请号：US14042623

    申请日：2013-09-30

    申请人： MICHAEL B. VINCENT ,  Zhiwei Gong

    发明人： MICHAEL B. VINCENT ,  Zhiwei Gong

    IPC分类号： H05K1/11 ,  H05K3/10 ,  H05K3/32 ,  H05K1/18

    CPC分类号： H01L23/3114 ,  H01L23/49805 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1815 ,  Y10T29/4913 ,  H01L2924/00

    摘要： Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.

    摘要翻译： 装置及其制造方法的实施例包括将第一和第二封装表面导体耦合到封装表面，并在封装表面导体之间具有导体内绝缘结构。 封装表面导体在封装表面露出的焊垫组之间延伸并电耦合。 包装表面导体的细长部分彼此平行并相邻。 导体内绝缘结构沿着整个平行和相邻的细长部分耦合在封装表面导体之间，并且导体内绝缘结构将封装表面导体的细长部分彼此电绝缘。 一些实施例可以结合堆叠的微电子封装来实现，该堆叠式微电子封装包括侧壁导体和导体间绝缘结构，并且使侧壁导体彼此电绝缘。