摘要:
A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.
摘要:
A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.
摘要:
Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.
摘要:
Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.
摘要:
Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.
摘要:
A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.
摘要:
A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors are attached to a major surface of a substrate that provides at least an electrical conduit from the ball conductor to an opposite major surface of the substrate. The substrate can also provide an interconnect between solder balls. The combination of solder balls and substrate is encapsulated in the semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while a portion of the ball conductors is exposed on the opposite major surface of the device package. The ball conductors and signal conduits provide signal-bearing pathways between the major surfaces of the package. Contacts created by the back grinded ball conductors are used to form a package-on-package structure by coupling with contacts from another package.
摘要:
A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.
摘要:
An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (1) using a double side adhesive tape (2), and then sequentially depositing an insulating layer (15) and a conductive shielding layer (16) before encapsulating the modules with a molding compound (17). After removing the adhesive tape (2) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (100) is formed over the exposed surface, where the circuit substrate includes shielding via structures (101-112) that are aligned with and electrically connected to the conductive shielding layer (16), thereby encircling and shielding the circuit module(s).
摘要:
An integrated conformal electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (1) using a double side adhesive tape (2), and then sequentially depositing an insulating layer (15) and a conductive shielding layer (16) before encapsulating the modules with a molding compound (17). After removing the adhesive tape (2) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (100) is formed over the exposed surface, where the circuit substrate includes shielding via structures (101-112) that are aligned with and electrically connected to the conductive shielding layer (16), thereby encircling and shielding the circuit module(s).