公开(公告)号：US09978705B2

公开(公告)日：2018-05-22

申请号：US15222873

申请日：2016-07-28

申请人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.

发明人： Guo-Cheng Liao ,  Chia-Ching Chen ,  Yi-Chuan Ding

IPC分类号： H01L23/48 ,  H01L23/00 ,  H05K3/00 ,  H01L23/498 ,  H01L21/48 ,  H05K3/20 ,  H05K3/46

CPC分类号： H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.

公开(公告)号：US09478500B2

公开(公告)日：2016-10-25

申请号：US14624331

申请日：2015-02-17

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chia-Ching Chen ,  Chin-Li Kao ,  Hung-Jen Chang ,  Tang-Yuan Chen ,  Wei-Hong Lai

IPC分类号： H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L21/683 ,  H05K1/11

CPC分类号： H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15331 ,  H05K3/205 ,  H05K2201/10378

摘要： Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.

摘要翻译： 这里描述了用于翘曲控制的插入式衬底设计，包括所述插入器衬底的半导体结构及其制造方法。 插入器基板限定空腔并且还包括加强结构，其中加强结构用于控制半导体封装结构的翘曲。

公开(公告)号：US09437565B2

公开(公告)日：2016-09-06

申请号：US14586735

申请日：2014-12-30

申请人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.

发明人： Guo-Cheng Liao ,  Chia-Ching Chen ,  Yi-Chuan Ding

IPC分类号： H01L23/52 ,  H01L23/00

CPC分类号： H01L24/16 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/08238 ,  H01L2224/10175 ,  H01L2224/11436 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/13008 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13647 ,  H01L2224/16012 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16235 ,  H01L2224/16503 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/3841 ,  H05K3/007 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.

摘要翻译： 本公开涉及包括半导体衬底，半导体芯片和导电材料的半导体封装结构。 半导体衬底包括绝缘层，导电电路层和导电凸块。 导电电路层从绝缘层的顶表面凹入，并且包括至少一个焊盘。 导电凸块设置在至少一个垫上。 导电凸块的侧表面，至少一个焊盘的顶表面和绝缘层的侧表面一起限定了容纳空间。 导电材料与导电凸块和半导体芯片电连接，导电材料的一部分设置在容纳空间中。

公开(公告)号：US09349611B2

公开(公告)日：2016-05-24

申请号：US13776567

申请日：2013-02-25

申请人： ADVANCED SEMICONDUCTOR ENGINEERING, INC.

发明人： Chia-Ching Chen ,  Yi-Chuan Ding

IPC分类号： H01L21/50 ,  H01L23/538 ,  H01L25/10 ,  H01L25/16 ,  H01L21/56 ,  H01L23/29 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L21/50 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/295 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05173 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16165 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/21 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/81192 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05193

摘要： A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced.

摘要翻译： 半导体封装包括一组螺柱凸块，其可以通过引线接合技术形成并且可以结合或接合到半导体元件以形成堆叠的封装组件。 由于将半导体元件接合到凸块凸块的过程可以在不回流的情况下进行，因此可以控制或降低由高温导致的不期望的变形。