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公开(公告)号：US09741675B2
公开(公告)日：2017-08-22
申请号：US14599366
申请日：2015-01-16
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Dao-Long Chen , Ping-Feng Yang , Chang-Chi Lee , Chien-Fan Chen
CPC classification number: H01L24/13 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/14 , H01L24/16 , H01L2224/0345 , H01L2224/0346 , H01L2224/03912 , H01L2224/0401 , H01L2224/05552 , H01L2224/05647 , H01L2224/05666 , H01L2224/0614 , H01L2224/1146 , H01L2224/1147 , H01L2224/1161 , H01L2224/11849 , H01L2224/119 , H01L2224/13007 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/1414 , H01L2224/16055 , H01L2224/16056 , H01L2224/81191 , H01L2924/351 , H01L2924/3511 , H01L2924/3512 , H01L2924/35121 , H01L2924/00012 , H01L2924/014 , H01L2924/00014
Abstract: The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.
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公开(公告)号：US11296030B2
公开(公告)日：2022-04-05
申请号：US16397530
申请日：2019-04-29
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Yu-Ju Liao , Chien-Fan Chen , Chien-Hao Wang
IPC: H05K3/46 , H01L23/538 , H01L21/48
Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.
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公开(公告)号：US12267961B2
公开(公告)日：2025-04-01
申请号：US18420528
申请日：2024-01-23
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Chien-Fan Chen , Chien-Hao Wang
IPC: H05K1/18 , H01L21/48 , H01L21/56 , H01L23/538
Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
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公开(公告)号：US11882660B2
公开(公告)日：2024-01-23
申请号：US18095511
申请日：2023-01-10
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Chien-Fan Chen , Chien-Hao Wang
IPC: H05K1/18 , H01L21/48 , H01L23/538 , H01L21/56
CPC classification number: H05K1/183 , H01L21/486 , H01L21/4857 , H01L21/568 , H01L23/5383 , H01L23/5386 , H01L2224/04105 , H01L2924/11 , H01L2924/15153 , H05K2201/10
Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
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公开(公告)号：US10950551B2
公开(公告)日：2021-03-16
申请号：US16397539
申请日：2019-04-29
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Yu-Ju Liao , Chien-Fan Chen , Chien-Hao Wang
IPC: H01L23/538 , H01L21/48 , H05K3/46 , H01L21/67 , H01L23/31
Abstract: An embedded component package structure including a dielectric structure and a component is provided. The component is embedded in the dielectric structure and is provided with a plurality of conductive pillars. The conductive pillars are exposed from an upper surface of the dielectric structure and have a first thickness and a second thickness, respectively, and the first thickness is not equal to the second thickness.
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Patent Agency Ranking
公开(公告)号：US09768139B2
公开(公告)日：2017-09-19
申请号：US15297691
申请日：2016-10-19
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Wan-Ting Chiu , Chien-Fan Chen
CPC classification number: H01L24/17 , H01L23/293 , H01L23/3157 , H01L23/3171 , H01L23/562 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/14 , H01L2224/022 , H01L2224/0401 , H01L2224/05552 , H01L2224/13014 , H01L2224/13016 , H01L2224/13023 , H01L2224/1411 , H01L2224/17107 , H01L2225/06513 , H01L2924/07025 , H01L2924/35
Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.
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公开(公告)号：US09508671B2
公开(公告)日：2016-11-29
申请号：US14691448
申请日：2015-04-20
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Wan-Ting Chiu , Chien-Fan Chen
CPC classification number: H01L24/17 , H01L23/293 , H01L23/3157 , H01L23/3171 , H01L23/562 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/14 , H01L2224/022 , H01L2224/0401 , H01L2224/05552 , H01L2224/13014 , H01L2224/13016 , H01L2224/13023 , H01L2224/1411 , H01L2224/17107 , H01L2225/06513 , H01L2924/07025 , H01L2924/35
Abstract: The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element and two pillar structures. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on the one bonding pad. The two pillar structures are symmetric and formed of a same material.
Abstract translation: 本公开涉及在半导体封装中有用的结合结构。 在一个实施例中，半导体器件包括半导体元件和两个支柱结构。 半导体元件具有表面并且包括邻近表面设置的至少一个焊盘。 两个支柱结构设置在一个焊盘上。 两个柱结构是对称的，由相同的材料形成。
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公开(公告)号：US11587881B2
公开(公告)日：2023-02-21
申请号：US16813369
申请日：2020-03-09
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Chien-Fan Chen , Yu-Ju Liao , Chu-Jie Yang , Sheng-Hung Shih
IPC: H01L23/538 , H01L23/498 , H01L21/48 , H01L25/065
Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.
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公开(公告)号：US11139179B2
公开(公告)日：2021-10-05
申请号：US16565064
申请日：2019-09-09
Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Inventor： Chien-Fan Chen , Yu-Ju Liao
Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure encapsulates the semiconductor chip and has a first thickness. The semiconductor chip having a second thickness, and the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extending into a first opening of the dielectric structure. The first opening exposes an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip.
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公开(公告)号：US11923285B2
公开(公告)日：2024-03-05
申请号：US17142198
申请日：2021-01-05
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Po-Jen Cheng , Chien-Fan Chen
IPC: H01L23/495 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/18
CPC classification number: H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L21/568 , H01L23/3128 , H01L23/3142 , H01L23/49816 , H01L23/49822 , H01L23/5385 , H01L23/5389 , H01L24/16 , H01L25/18 , H01L23/3135 , H01L2224/16227
Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.
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