公开(公告)号：US10249593B2

公开(公告)日：2019-04-02

申请号：US15310684

申请日：2015-06-22

Applicant: Agency for Science, Technology and Research

Inventor： Sunil Wickramanayaka ,  Ling Xie ,  Jerry Jie Li Aw

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like plurality of contacts on the other of the chip and the wafer. After formation, a contact surface of each post is planarized, the respective planarized contact surface having a surface roughness height. A bonding material is then applied to at least one of the chip in a thickness no greater than the surface roughness height of the contact surface. The posts are then temporarily bonded to the contacts using the bonding material to stabilize a position of the chip relative to the wafer for permanent diffusion bonding of the chip to the wafer.

公开(公告)号：US20170084570A1

公开(公告)日：2017-03-23

申请号：US15310684

申请日：2015-06-22

Applicant: Agency for Science, Technology and Research

Inventor： Sunil Wickramanayaka ,  Ling Xie ,  Jerry Jie Li Aw

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/119 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/16225 ,  H01L2224/81022 ,  H01L2224/8109 ,  H01L2224/81097 ,  H01L2224/81099 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/8183 ,  H01L2224/81986 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/9205

Abstract: A method for chip on wafer bonding is provided. The method includes the formation of a plurality of posts on at least one of a chip and a wafer, and a like plurality of contacts on the other of the chip and the wafer. After formation, a contact surface of each post is planarized, the respective planarized contact surface having a surface roughness height. A bonding material is then applied to at least one of the chip in a thickness no greater than the surface roughness height of the contact surface. The posts are then temporarily bonded to the contacts using the bonding material to stabilize a position of the chip relative to the wafer for permanent diffusion bonding of the chip to the wafer.

公开(公告)号：US20160155720A1

公开(公告)日：2016-06-02

申请号：US14904670

申请日：2014-07-16

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Sunil Wickramanayaka

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L24/743 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/27515 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/7501 ,  H01L2224/75102 ,  H01L2224/7511 ,  H01L2224/75184 ,  H01L2224/75264 ,  H01L2224/753 ,  H01L2224/7598 ,  H01L2224/81002 ,  H01L2224/81093 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81209 ,  H01L2224/81903 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8309 ,  H01L2224/83093 ,  H01L2224/83097 ,  H01L2224/8312 ,  H01L2224/83193 ,  H01L2224/83209 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83907 ,  H01L2224/83911 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method includes the steps of placing at least one chip on a wafer to form an integrated product, forming a film on the integrated product, such that the integrated product is substantially fluid-tight, and exerting a predetermined positive pressure on the film during permanent bonding of the at least one chip to the wafer. The method further includes the step of removing the film from the integrated product after permanent bonding of the at least one chip to the wafer.

Abstract translation: 提供了一种用于芯片到晶片集成的装置和方法。 该装置包括涂覆模块，粘合模块和清洁模块。 该方法包括以下步骤：将至少一个芯片放置在晶片上以形成集成的产品，在集成产品上形成膜，使得集成产品基本上是流体密封的，并且在永久性地在膜上施加预定的正压力 将至少一个芯片接合到晶片。 该方法还包括在将至少一个芯片永久地接合到晶片之后，从集成产品中去除膜的步骤。

公开(公告)号：US11508619B2

公开(公告)日：2022-11-22

申请号：US16962146

申请日：2019-01-24

Applicant: Agency for Science, Technology and Research

Inventor： Hongyu Li ,  Ling Xie ,  Ser Choong Chong ,  Sunil Wickramanayaka

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00

Abstract: Various embodiments may provide a method of forming an electrical connection structure. The method may include forming a cavity on a front surface of a substrate, the substrate including an electrically conductive pad, by etching through the electrically conductive pad. The method may also include forming one or more dielectric liner layers covering an inner surface of the cavity. The method may further include forming a via hole extending from the cavity by etching through the one or more dielectric liner layers, forming one or more further dielectric liner layers covering an inner surface of the via hole. The method may additionally include depositing a suitable electrically conductive material into the cavity and the via hole to form a conductive via having a first portion in the cavity and a second portion in the via hole, a diameter of the first portion different from a diameter of the second portion.

公开(公告)号：US10134607B2

公开(公告)日：2018-11-20

申请号：US15321701

申请日：2015-07-09

Applicant: Agency for Science, Technology and Research

Inventor： Vivek Chidambaram ,  Sunil Wickramanayaka ,  Jinghui Xu ,  Zhipeng Ding ,  Li Yan Siow

IPC: B23K20/02 ,  B81C3/00 ,  C25D3/48 ,  H01L23/48 ,  H05K1/11 ,  H01L23/373 ,  H01L23/15 ,  H01L21/58 ,  H01L21/50 ,  B23K35/00 ,  H01L23/488

Abstract: A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature.

公开(公告)号：US20170309584A1

公开(公告)日：2017-10-26

申请号：US15518064

申请日：2015-10-23

Applicant: Agency for Science, Technology and Research

Inventor： Ling Xie ,  Sunil Wickramanayaka

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/13 ,  H01L23/48 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05109 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/11009 ,  H01L2224/1146 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11822 ,  H01L2224/1184 ,  H01L2224/11903 ,  H01L2224/13014 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1369 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/8112 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/8182 ,  H01L2224/81825 ,  H01L2224/8185 ,  H01L2224/81856 ,  H01L2224/81905 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2224/81 ,  H01L2924/00014

Abstract: A method for bonding a first substrate and a second substrate, the first substrate having at least one first connection extending from one side of the first substrate, the method comprising fabricating a first adhesive material around and along a height of the at least one first connection; and bonding the at least one first connection, the first adhesive material, and the second substrate.

公开(公告)号：US09613928B2

公开(公告)日：2017-04-04

申请号：US14904670

申请日：2014-07-16

Applicant: Agency for Science, Technology and Research

Inventor： Sunil Wickramanayaka

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L21/563 ,  H01L24/743 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/27515 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/7501 ,  H01L2224/75102 ,  H01L2224/7511 ,  H01L2224/75184 ,  H01L2224/75264 ,  H01L2224/753 ,  H01L2224/7598 ,  H01L2224/81002 ,  H01L2224/81093 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81209 ,  H01L2224/81903 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8309 ,  H01L2224/83093 ,  H01L2224/83097 ,  H01L2224/8312 ,  H01L2224/83193 ,  H01L2224/83209 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/83907 ,  H01L2224/83911 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An apparatus and a method for chip-to-wafer integration is provided. The apparatus includes a coating module, a bonding module and a cleaning module. The method includes the steps of placing at least one chip on a wafer to form an integrated product, forming a film on the integrated product, such that the integrated product is substantially fluid-tight, and exerting a predetermined positive pressure on the film during permanent bonding of the at least one chip to the wafer. The method further includes the step of removing the film from the integrated product after permanent bonding of the at least one chip to the wafer.