公开(公告)号：US11756844B2

公开(公告)日：2023-09-12

申请号：US17170120

申请日：2021-02-08

申请人： Micron Technology, Inc.

发明人： Wei Zhou ,  Bret K. Street ,  Mark E. Tuttle

IPC分类号： H01L23/532 ,  H01L23/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L25/00

CPC分类号： H01L23/10 ,  H01L23/04 ,  H01L24/17 ,  H01L24/67 ,  H01L24/70 ,  H01L24/73 ,  H01L24/81 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/8109 ,  H01L2224/81075 ,  H01L2224/8182 ,  H01L2224/81122 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/01029 ,  H01L2924/3025 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate; a die attached over the substrate; and a metal enclosure continuously encircling a space and extending vertically between the substrate and the die.

公开(公告)号：US09679875B2

公开(公告)日：2017-06-13

申请号：US15135599

申请日：2016-04-22

申请人： International Business Machines Corporation

发明人： Peter A. Gruber ,  Katsuyuki Sakuma ,  Da-Yuan Shih

IPC分类号： H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0612 ,  H01L2224/065 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/1141 ,  H01L2224/1144 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/14104 ,  H01L2224/16012 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81022 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/811 ,  H01L2224/8112 ,  H01L2224/81201 ,  H01L2224/8121 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81203 ,  H01L2924/01047 ,  H01L2924/01029

摘要： A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

公开(公告)号：US20170069595A1

公开(公告)日：2017-03-09

申请号：US15257427

申请日：2016-09-06

申请人： Invensas Corporation

发明人： Belgacem Haba

IPC分类号： H01L23/00

CPC分类号： H01L24/83 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05687 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13193 ,  H01L2224/1403 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16146 ,  H01L2224/271 ,  H01L2224/2733 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/27849 ,  H01L2224/29027 ,  H01L2224/29028 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75102 ,  H01L2224/8109 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8309 ,  H01L2224/83101 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/381 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0675 ,  H01L2924/0635 ,  H01L2924/00012 ,  H01L2924/069 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/27

摘要： 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

摘要翻译： 提供了微电子部件的3D连接和导电自调节各向异性矩阵。 在一个实施方案中，粘合剂基质自动地在具有电接触的两个表面之间进行电连接，并将两个表面粘合在一起。 粘合剂基体中的导电构件对准以在两个表面中的每一个上的至少部分对准的触点之间自动建立电连接，同时在缺少对准的触点的两个表面的部分之间提供非导电粘附。 一个示例性方法包括在待接合的两个表面之间形成粘合剂基体，包括在粘合剂介质中各向异性排列的导电构件，然后将两个表面压在一起，以自动连接在两个表面上至少部分对准的对应的电触头。 基体中的粘合剂介质将两个表面固定在一起。

公开(公告)号：US09219047B2

公开(公告)日：2015-12-22

申请号：US14168897

申请日：2014-01-30

申请人： TOHOKU-MICROTEC CO., LTD

发明人： Makoto Motoyoshi

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/14 ,  H01L23/147 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/02126 ,  H01L2224/0215 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/09517 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1134 ,  H01L2224/11444 ,  H01L2224/1147 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81007 ,  H01L2224/8109 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81986 ,  H01L2224/95146 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/01322 ,  H01L2924/15192 ,  H01L2924/00 ,  H01L2224/16225 ,  H01L2924/01013 ,  H01L2924/01032 ,  H01L2924/01051 ,  H01L2924/0105 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81

摘要： A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

摘要翻译： 堆叠式装置包括包括多个布线平台和多个壁块图案的下部芯片，每个壁块图案被分配在除了设置布线平台的位置之外的位置处，每个壁块图案 具有倾斜平面，从布线平台的阵列的参考平面测量的每个壁块图案的高度高于布线平台，并且上部芯片包括相应于位置的多个布线凸块 分别布线着陆，以及分别对应于壁块图案的位置分配的多个锥形凸块。

公开(公告)号：US09016342B2

公开(公告)日：2015-04-28

申请号：US13184084

申请日：2011-07-15

申请人： Kazuhiko Kobayashi

发明人： Kazuhiko Kobayashi

IPC分类号： B32B37/10 ,  H01L23/00

CPC分类号： H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/95 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75102 ,  H01L2224/75252 ,  H01L2224/753 ,  H01L2224/75313 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/7532 ,  H01L2224/755 ,  H01L2224/75502 ,  H01L2224/75704 ,  H01L2224/75755 ,  H01L2224/75756 ,  H01L2224/75804 ,  H01L2224/7598 ,  H01L2224/75984 ,  H01L2224/81048 ,  H01L2224/8109 ,  H01L2224/81093 ,  H01L2224/83048 ,  H01L2224/8309 ,  H01L2224/83093 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/95093 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/00

摘要： The bonding apparatus is capable of effectively increasing temperature of a substrate and reducing occurrence of position gaps and poor connection in a process of flip-chip-bonding semiconductor devices to the substrate. The bonding apparatus comprises: a supporting unit for supporting the substrate, on which the semiconductor devices have been adhered by a non-conductive; and a heating/pressing unit for heating and pressing the substrate, the heating/pressing unit having a built-in heat source and a clamping face, onto which the substrate supported by the supporting unit is pressed. The substrate supported by the supporting unit is moved toward the clamping face of the heating/pressing unit so as to preheat the substrate and the semiconductor devices by radiation heat. Then, the semiconductor devices are pressed onto the clamping face of the heating/pressing unit so as to cure the non-conductive adhesive and bond bumps of the semiconductor devices to terminal sections of the substrate.

摘要翻译： 接合装置能够有效地增加衬底的温度并减少在将半导体器件倒装芯片接合到衬底的工艺中位置间隙的发生和连接不良。 接合装置包括：用于支撑基板的支撑单元，半导体器件已经通过非导电粘附在该基板上; 以及用于加热和加压基板的加热/加压单元，加热/加压单元具有内置的热源和夹紧面，由支撑单元支撑的基板被压在该加热/加压单元上。 由支撑单元支撑的基板朝向加热/加压单元的夹紧面移动，以便通过辐射热预热基板和半导体器件。 然后，将半导体器件按压到加热/加压单元的夹紧面上，以固化不导电粘合剂并将半导体器件的凸起接合到衬底的端子部分。

公开(公告)号：US20140217593A1

公开(公告)日：2014-08-07

申请号：US14174178

申请日：2014-02-06

申请人： National Chiao Tung University

发明人： Chih CHEN ,  Taochi LIU ,  Yi-Sa HUANG ,  Chien-Min LIU

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L23/49866 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/03826 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16145 ,  H01L2224/27462 ,  H01L2224/29005 ,  H01L2224/29023 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/32145 ,  H01L2224/75272 ,  H01L2224/75704 ,  H01L2224/75705 ,  H01L2224/81011 ,  H01L2224/8109 ,  H01L2224/81097 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2224/83011 ,  H01L2224/8309 ,  H01L2224/83097 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83208 ,  H01L2224/8321 ,  H01L2224/8383 ,  H01L2224/83895 ,  H01L2224/94 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/81

摘要： An electrical connecting element for connecting a first substrate and a second substrate and a method for manufacturing the same are disclosed. The method of the present invention comprises: (A) providing a first substrate and a second substrate, wherein a first copper film is formed on the first substrate, a first metal film is formed on the second substrate, a first connecting surface of the first copper film has a (111)-containing surface, and the first metal film has a second connecting surface; and (B) connecting the first copper film and the first metal film to form an interconnect, wherein the first connecting surface of the first copper film is faced to the second connecting surface of the first metal film.

摘要翻译： 公开了一种用于连接第一基板和第二基板的电连接元件及其制造方法。 本发明的方法包括：（A）提供第一基板和第二基板，其中在第一基板上形成第一铜膜，在第二基板上形成第一金属膜，第一基板上的第一连接表面 铜膜具有含（111）表面，第一金属膜具有第二连接面; 和（B）连接第一铜膜和第一金属膜以形成互连，其中第一铜膜的第一连接表面面对第一金属膜的第二连接表面。

公开(公告)号：US08757474B2

公开(公告)日：2014-06-24

申请号：US13806907

申请日：2011-06-24

申请人： Hideyuki Abe ,  Kazuaki Mawatari

发明人： Hideyuki Abe ,  Kazuaki Mawatari

IPC分类号： B23K31/02

CPC分类号： B23K3/0607 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/20 ,  B23K1/206 ,  B23K3/04 ,  B23K3/082 ,  B23K31/02 ,  B23K35/38 ,  B23K2101/40 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75101 ,  H01L2224/7515 ,  H01L2224/75272 ,  H01L2224/81002 ,  H01L2224/81011 ,  H01L2224/81014 ,  H01L2224/81019 ,  H01L2224/81054 ,  H01L2224/8109 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83104 ,  H01L2924/01322 ,  H05K3/305 ,  H05K3/3436 ,  H05K13/0465 ,  H05K2203/083 ,  H05K2203/085 ,  H05K2203/087 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/00

摘要： A soldering method capable of alleviating positional displacement between substrates even though a step of removing flux can be omitted is provided.A temporary bonding agent 55 is applied onto multiple substrates 50a, 50b, and a heater 33 heats the substrates while the substrates are temporarily bonded with the temporary bonding agent 55 interposed therebetween, and before the solder 54 is melted or while the solder 54 is melted, the temporary bonding agent 55 is evaporated, and the substrates 50a, 50b are bonded with solder with the melted solder 54 interposed therebetween.

摘要翻译： 提供了能够减轻基板之间的位置偏移的焊接方法，即使可以省略去除焊剂的步骤。 临时粘合剂55被施加到多个基板50a，50b上，并且加热器33加热基板，同时基板临时粘合在其间插入临时粘合剂55，并且在焊料54熔化之前或焊料54熔融之前 ，临时粘合剂55蒸发，并且基板50a，50b与焊料接合，熔融的焊料54插入其间。

公开(公告)号：US20120193752A1

公开(公告)日：2012-08-02

申请号：US13016994

申请日：2011-01-29

申请人： Sampath Purushothaman ,  Roy Rongqing Yu

发明人： Sampath Purushothaman ,  Roy Rongqing Yu

IPC分类号： H01L27/12 ,  H01L21/60

CPC分类号： H01L21/76897 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/544 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L2221/68372 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/11002 ,  H01L2224/1148 ,  H01L2224/11616 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/8013 ,  H01L2224/81005 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/8109 ,  H01L2224/81093 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81209 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.

摘要翻译： 通过这种方法制造的工艺和最终的制品包括将包含硅绝缘体（SOI）的顶部硅晶片中的将底部硅晶片中的底部器件层连接到顶部器件层中的底部器件层所需的通孔形成， 晶圆。 通孔以这样的方式设置，使得它们从顶部晶片的线（MOL）互连的中间延伸到SOI晶片的掩埋氧化物（BOX）层，其中提供了适当的绝缘以将它们与SOI器件层隔离开。

公开(公告)号：US07745321B2

公开(公告)日：2010-06-29

申请号：US11972793

申请日：2008-01-11

申请人： Alfred Martin ,  Barbara Hasler ,  Martin Franosch ,  Klaus-Guenter Oppermann

发明人： Alfred Martin ,  Barbara Hasler ,  Martin Franosch ,  Klaus-Guenter Oppermann

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H05K3/3452 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06136 ,  H01L2224/10125 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11422 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/8109 ,  H01L2224/81205 ,  H01L2224/8123 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3484 ,  H05K2201/0989 ,  H05K2201/2081 ,  H05K2203/043 ,  H01L2924/00014 ,  H01L2224/05552

摘要： An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.

摘要翻译： 一种集成电路，包括衬底和衬底上的结构化层。 结构化层包括到基板的开口，在基板上的第一场和第二场，其中第一场和第二场至少部分地与开口重叠。 集成电路还包括第一场区域中的第一材料和第二场区域中的第二材料。 第一种材料阻碍焊料材料的润湿，第二种材料通过焊料材料而被润湿。

公开(公告)号：US20090137082A1

公开(公告)日：2009-05-28

申请号：US12292378

申请日：2008-11-18

申请人： Yoichiro Kurita

发明人： Yoichiro Kurita

IPC分类号： H01L21/60 ,  B23K31/02 ,  B23K1/20

CPC分类号： B23K1/0016 ,  B23K2101/40 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27515 ,  H01L2224/27552 ,  H01L2224/2761 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/75745 ,  H01L2224/7598 ,  H01L2224/81048 ,  H01L2224/81065 ,  H01L2224/8109 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81906 ,  H01L2224/81907 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01082 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/16145 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A manufacturing method for manufacturing an electronic device includes a first electronic component and a second electronic component; and a bond part for the first electronic component joined to another bond part for the second electronic component. In a first process of this manufacturing method, the metallic bond part for the first electronic component is placed directly against the metallic bond part for the second electronic component, pressure is applied to the first electronic component and the second electronic component and, after metallically joining the above two bond parts, the pressure applied to the first electronic component and the second electronic component is released. In a second process in the manufacturing method, a clamping member affixes the relative positions of the joined first electronic component and second electronic component, and heats the first electronic component and the second electronic component to maintain a specified temperature.

摘要翻译： 一种电子设备的制造方法，包括：第一电子部件和第二电子部件; 以及与第二电子部件的另一接合部接合的第一电子部件的接合部。 在该制造方法的第一工序中，将第一电子部件的金属接合部直接配置在第二电子部件的金属接合部上，对第一电子部件和第二电子部件施加压力，在金属接合 上述两个粘合部分，释放施加到第一电子部件和第二电子部件的压力。 在制造方法的第二工序中，夹持构件固定连接的第一电子部件和第二电子部件的相对位置，并加热第一电子部件和第二电子部件，以维持规定的温度。