公开(公告)号：US4700466A

公开(公告)日：1987-10-20

申请号：US825544

申请日：1986-02-03

申请人： Akio Nakagawa ,  Hiromichi Ohashi ,  Tsuneo Ogura ,  Masaru Shimbo

发明人： Akio Nakagawa ,  Hiromichi Ohashi ,  Tsuneo Ogura ,  Masaru Shimbo

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/18 ,  H01L21/20 ,  H01L21/306 ,  H01L21/336 ,  H01L27/12 ,  H01L29/74 ,  H01L29/861 ,  H01L21/461

CPC分类号： H01L21/02052 ,  H01L21/187

摘要： A method of manufacturing a semiconductor device, wherein a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer is formed. A first silicon substrate, having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, is brought into contact with a second silicon substrate which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other. The contacting substrates are then placed in a clean atmosphere so that virtually no foreign substances are present therebetween, and annealed at a temperature of not less than 200.degree. C. so as to bond them together, thereby forming the second impurity-doped layer consisting of the third impurity doped layer and the second silicon substrate.

摘要翻译： 一种制造半导体器件的方法，其中形成具有第一杂质掺杂层和杂质浓度高于第一杂质掺杂层的第二杂质掺杂层的半导体晶片。 具有第一杂质掺杂层和第三杂质掺杂层的第一硅衬底，其具有比第一杂质掺杂层高的杂质浓度和与第二杂质掺杂层相同的导电类型，以及 其表面经镜面抛光与第二硅衬底接触，第二硅衬底的杂质浓度高于第一杂质掺杂层的杂质浓度并且具有与第二杂质掺杂层相同的导电类型，并且其表面为 镜面抛光，使得其镜面抛光表面彼此接触。 然后将接触的基材放置在清洁的气氛中，实际上不存在异物，并在不低于200℃的温度下进行退火，以将它们结合在一起，由此形成第二杂质掺杂层，由 第三杂质掺杂层和第二硅衬底。

公开(公告)号：US5477065A

公开(公告)日：1995-12-19

申请号：US191132

申请日：1994-01-24

申请人： Akio Nakagawa ,  Tsuneo Ogura

发明人： Akio Nakagawa ,  Tsuneo Ogura

IPC分类号： H01L21/8234 ,  H01L21/98 ,  H01L23/433 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L27/00 ,  H01L27/01 ,  H01L27/082 ,  H01L27/088 ,  H01L27/12 ,  H01L27/15 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/786 ,  H01L31/12 ,  H01L29/749

CPC分类号： H01L29/7317 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/7436 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/48463 ,  H01L2224/73227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A composite integrated circuit device includes a semiconductor element chip, a positioning guide formed on the semiconductor element chip, and an electronic element set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide and mounted thereon. Also disclosed is are lateral, thin film devices with tapered shapes to reduce breakdown.

摘要翻译： 复合集成电路器件包括半导体元件芯片，形成在半导体元件芯片上的定位引导件和通过定位引导件以自对准方式设置在半导体元件芯片上的预设位置的电子元件并安装在其上 。 还公开了具有锥形形状以减少击穿的横向薄膜装置。

公开(公告)号：US5463231A

公开(公告)日：1995-10-31

申请号：US353385

申请日：1994-12-02

申请人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

发明人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

IPC分类号： H01L27/06 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L27/0617 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

公开(公告)号：US5332920A

公开(公告)日：1994-07-26

申请号：US850964

申请日：1992-03-11

申请人： Akio Nakagawa ,  Kazuyoshi Furukawa ,  Tsuneo Ogura ,  Katsujiro Tanzawa

发明人： Akio Nakagawa ,  Kazuyoshi Furukawa ,  Tsuneo Ogura ,  Katsujiro Tanzawa

IPC分类号： H01L21/761 ,  H01L21/762 ,  H01L21/763 ,  H01L27/088 ,  H01L27/12 ,  H01L29/739 ,  H01L29/70

CPC分类号： H01L21/76264 ,  H01L21/761 ,  H01L21/76297 ,  H01L21/763 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7394 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286 ,  H01L2924/10158

摘要： A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

摘要翻译： 绝缘隔离衬底包括：第一半导体晶片;第二半导体晶片，其在第一半导体晶片上具有第一绝缘层，第二绝缘层插入在第二半导体晶片之间，形成在第二半导体晶片上的半导体层，形成在半导体层中的第一沟槽和第二半导体层 晶片，以便到达第一绝缘层，从而隔离半导体层和第二半导体晶片，以及形成在第一凹槽的侧面上或嵌入在第一凹槽中的第二绝缘层。 在该绝缘隔离衬底中，在由第一沟槽隔离的区域中形成高击穿电压元件和低击穿电压元件。

公开(公告)号：US4994696A

公开(公告)日：1991-02-19

申请号：US371275

申请日：1989-06-26

申请人： Tsuneo Ogura ,  Akio Nakagawa

发明人： Tsuneo Ogura ,  Akio Nakagawa

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/744 ,  H01L29/749 ,  H03K17/732

CPC分类号： H01L29/102 ,  H01L29/0834 ,  H01L29/744 ,  H01L29/749 ,  H03K17/732

摘要： A turn-on/off driving method for an insulated gate thyristor which has a first gate electrode insulatively provided above a first base layer and functioning as the gate of MOSFET, and a second gate electrode formed on the second base layer. To execute the turn-off driving operation, a first voltage is applied to the second gate electrode to produce reverse biasing between the second emitter layer and the second base layer, thereby to quench this thyristor. A second voltge which renders the transistor nonconductive is applied the first gate electrode before the application of the first voltage. The turn-on driving operation of the thyristor may be performed by using the first gate electrode.

公开(公告)号：US4866315A

公开(公告)日：1989-09-12

申请号：US161095

申请日：1988-02-26

申请人： Tsuneo Ogura ,  Akio Nakagawa

发明人： Tsuneo Ogura ,  Akio Nakagawa

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/744 ,  H01L29/749 ,  H03K17/732

CPC分类号： H01L29/102 ,  H01L29/0834 ,  H01L29/744 ,  H01L29/749 ,  H03K17/732

摘要： A turn-on/off driving technique for an insulated gate thyristor which has a first gate electrode insulatively provided above a first base layer and functioning as a gate of MOSFET, and a second gate electrode formed on the second base layer. To drive the turn-on of the thyristor, a first voltage for rendering the MOSFET conductive is applied to the first gate electrode, while substantially simultaneously a second voltage for producing forward biasing between the second base layer and a second emitter layer is applied to the second gate electrode. To turn-off drive the thyristor, a third voltage for reverse biasing between the second emitter layer and the second base layer to stop the operation of the thyristor is applied to the second gate, while the MOSFET is kept conductive. The thyristor starts turning off in response to the voltage application. At this time, charge carriers exhausted from the second emitter layer are allowed to flow into the first base layer through the channel region of the MOSFET, thereby suppressing the local concentration of the turn-off current in the thyristor.

公开(公告)号：US4821083A

公开(公告)日：1989-04-11

申请号：US101790

申请日：1987-09-28

申请人： Tsuneo Ogura ,  Katsuhiko Takigami ,  Akio Nakagawa ,  Tomokazu Domon

发明人： Tsuneo Ogura ,  Katsuhiko Takigami ,  Akio Nakagawa ,  Tomokazu Domon

IPC分类号： H01L29/08 ,  H01L29/744 ,  H03K17/00 ,  H03K17/732

CPC分类号： H01L29/0834 ,  H01L29/744 ,  H03K17/732 ,  H03K2217/0036

摘要： A gate turn-off thyristor drive system with low power loss when it is in the turn-off mode, is disclosed. A first turn-off pulse of a predetermined amplitude is applied to a first gate electrode. A second turn-off pulse is applied to a second gate electrode. An amplitude of the second turn-off pulse is smaller in absolute value than that of the first turn-off pulse. The fall time of the anode current at the time of turn-off is reduced, and the initial value of the tail current of the anode current is reduced. The power loss as the product of the anode voltage and the anode current is reduced.

摘要翻译： 公开了一种在关闭模式时具有低功率损耗的栅极截止晶闸管驱动系统。 将预定幅度的第一关断脉冲施加到第一栅电极。 第二截止脉冲被施加到第二栅电极。 第二截止脉冲的幅度的绝对值小于第一截止脉冲的幅度。 在关断时的阳极电流的下降时间减少，阳极电流的尾电流的初始值减小。 作为阳极电压和阳极电流的乘积的功率损耗减小。

公开(公告)号：US5994739A

公开(公告)日：1999-11-30

申请号：US478654

申请日：1995-06-07

申请人： Akio Nakagawa ,  Tsuneo Ogura

发明人： Akio Nakagawa ,  Tsuneo Ogura

IPC分类号： H01L21/98 ,  H01L23/433 ,  H01L23/538 ,  H01L25/16 ,  H01L25/18 ,  H01L27/12 ,  H01L29/739 ,  H01L27/01

CPC分类号： H01L29/7394 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/1203 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/73227 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： An integrated circuit device comprising an active layer of a first conductivity type insulatively disposed over a semiconductor substrate, a lateral bipolar transistor fabricated in the active layer, the lateral bipolar transistor comprising a first base layer of a second conductivity type which is formed in the active layer, an emitter layer of the first conductivity, and a collector of the first conductivity which is formed in the active layer on a lateral side of the first base layer, a MOS transistor fabricated in the active layer, the MOS transistor comprising a second base layer of the second conductivity type, a source layer of the first conductivity type which is formed in the second base layer, a drain layer of the first conductivity type which is formed in the active layer, and a gate electrode insulatively disposed over the second base layer between the source layer and the drain layer, and an isolation layer formed in the active layer for separating the bipolar transistor and the MOS transistor from each other.

摘要翻译： 一种集成电路装置，包括绝缘地设置在半导体衬底上的第一导电类型的有源层，在有源层中制造的横向双极晶体管，所述横向双极晶体管包括形成在有源层中的第二导电类型的第一基极层 层，第一导电性的发射极层和形成在第一基极层的侧面的有源层中的第一导电性的集电体，制造在有源层中的MOS晶体管，所述MOS晶体管包括第二基极 第二导电类型的层，形成在第二基极层中的第一导电类型的源极层，形成在有源层中的第一导电类型的漏极层和绝缘地设置在第二基极上的栅电极 源极层和漏极层之间的层，以及形成在用于分离双极晶体管a的有源层中的隔离层 并将MOS晶体管彼此连接起来。

公开(公告)号：US5714782A

公开(公告)日：1998-02-03

申请号：US745248

申请日：1996-11-08

申请人： Akio Nakagawa ,  Tsuneo Ogura

发明人： Akio Nakagawa ,  Tsuneo Ogura

IPC分类号： H01L21/8234 ,  H01L21/98 ,  H01L23/433 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L27/00 ,  H01L27/01 ,  H01L27/082 ,  H01L27/088 ,  H01L27/12 ,  H01L27/15 ,  H01L29/73 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/786 ,  H01L31/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7317 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/7436 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/48463 ,  H01L2224/73227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A composite integrated circuit device includes a semiconductor element chip, a positioning guide formed on the semiconductor element chip, and an electronic element set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide and mounted thereon.

摘要翻译： 复合集成电路器件包括半导体元件芯片，形成在半导体元件芯片上的定位引导件和通过定位引导件以自对准方式设置在半导体元件芯片上的预设位置的电子元件并安装在其上 。

公开(公告)号：US5144401A

公开(公告)日：1992-09-01

申请号：US386763

申请日：1989-07-31

申请人： Tsuneo Ogura ,  Akio Nakagawa

发明人： Tsuneo Ogura ,  Akio Nakagawa

IPC分类号： H01L29/744 ,  H01L29/749

CPC分类号： H01L29/749 ,  H01L29/744

摘要： A thyristor is disclosed which has a laminated structure of a first emitter layer of n.sup.+ conductivity type, a first base layer of p type, a second base layer of p.sup.- type, a second emitter layer of n type, and a second emitter layer of p.sup.+ type. The first base layer has a first exposed surface portion which is in lateral contact with the first emitter layer, and a second exposed surface portion which is in lateral contact with the second base layer. The second surface portion defines a layer portion of the second base layer which is positioned between the first base layer and the second emitter layer. An anode electrode is connected to said second emitter layer, whereas a cathode electrode is connected to the second base layer and the first emitter layer. A first gate electrode is formed on the first surface portion of the first base layer. A second gate electrode is insulatively disposed above the second surface portion of the first base layer to form a MOSFET together with the first base layer and the second emitter layer. The layer portion of the second base layer serves as a channel region of the MOSFET.

摘要翻译： 公开了一种晶闸管，其具有n +导电类型的第一发射极层，p型的第一基极层，p型的第二基极层，n型的第二发射极层和n型的第二发射极层 p +型。 第一基层具有与第一发射极层侧向接触的第一暴露表面部分和与第二基底层侧向接触的第二暴露表面部分。 第二表面部分限定位于第一基底层和第二发射体层之间的第二基底层的层部分。 阳极电极连接到所述第二发射极层，而阴极连接到第二基极层和第一发射极层。 第一栅电极形成在第一基层的第一表面部分上。 第二栅电极被绝对地设置在第一基极层的第二表面部分上方，以与第一基极层和第二发射极层一起形成MOSFET。 第二基极层的层部分用作MOSFET的沟道区。