公开(公告)号：US20060249761A1

公开(公告)日：2006-11-09

申请号：US10539008

申请日：2003-12-16

申请人： Akira Inoue ,  Masahiko Hata

发明人： Akira Inoue ,  Masahiko Hata

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/7371 ,  H01L29/1004

摘要： In an epitaxial substrate comprising a bipolar transistor structure having a collector layer (3), base layer (4) and emitter layer (5) on a GaAs substrate (2), the base layer (4) is configured a lower base layer (41) having a required carrier concentration, an upper base layer (42), and a low carrier concentration layer (43) provided between the lower base layer (41) and the upper base layer (42) that has a ballast effect. The lower base layer (41) or the upper base layer (42) may be omitted. The higher the temperature of the low carrier concentration layer (43) portion is, the easier it is for electrons to pass therethrough, which has the effect of raising the amplification factor, thereby helping the transistor heat stability characteristics.

摘要翻译： 在包括在GaAs衬底（2）上具有集电极层（3），基底层（4）和发射极层（5））的双极晶体管结构的外延衬底中，基底层（4）被构造为下部基底层 ）具有设置在具有镇流效应的下基底层（41）和上基底层（42）之间的上基底层（42）和低载流子浓度层（43）。 可以省略下基层（41）或上基层（42）。 低载流子浓度层（43）部分的温度越高，电子越容易通过，这具有提高放大系数的作用，从而有助于晶体管的热稳定性。

公开(公告)号：US20060180833A1

公开(公告)日：2006-08-17

申请号：US10539006

申请日：2003-12-16

申请人： Akira Inoue ,  Masahiko Hata ,  Yasuyuki Kurita

发明人： Akira Inoue ,  Masahiko Hata ,  Yasuyuki Kurita

IPC分类号： H01L31/109

CPC分类号： H01L29/7371 ,  H01L29/0821

摘要： In an epitaxial substrate (20) comprising a collector layer (22), a base layer (23) and an emitter layer (24) formed on a semi-insulating GaAs substrate (21), a hole barrier layer (22C) is provided in the collector layer (22) to prevent influx of holes from the base layer (23), whereby the flow of collector current is suppressed when the collector current density rises and electron velocity is saturated, suppressing thermal runaway of the collector current without a ballast resistance or the like. Also, thermal runaway of the collector current is suppressed by providing an additional layer (2C) for generating, in the conduction band, an electron barrier by means of electrons accumulated in the collector layer (2) when the collector current density rises.

摘要翻译： 在包括集电极层（22），形成在半绝缘GaAs衬底（21）上的基极层（23）和发射极层（24））的外延衬底（20）中，提供了空穴阻挡层（22C） 在集电体层（22）中，为了防止从基底层（23）流入空穴，由此当集电极电流密度上升，电子速度饱和时，集电极电流的流动受到抑制，抑制了没有镇流器的集电极电流的热失控 电阻等。 此外，通过设置用于在集电极电流密度上升时通过积聚在集电极层（2）中的电子在导带中产生电子势垒的附加层（2C）来抑制集电极电流的热失控。

公开(公告)号：US08890213B2

公开(公告)日：2014-11-18

申请号：US13301272

申请日：2011-11-21

申请人： Sadanori Yamanaka ,  Masahiko Hata ,  Noboru Fukuhara

发明人： Sadanori Yamanaka ,  Masahiko Hata ,  Noboru Fukuhara

IPC分类号： H01L29/70 ,  H01L29/66 ,  H01L31/0304 ,  H01L29/737 ,  H01L21/02 ,  H01L31/0312 ,  H01L31/18

CPC分类号： H01L29/7371 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66318 ,  H01L31/0304 ,  H01L31/03044 ,  H01L31/0312 ,  H01L31/1852 ,  Y02E10/544 ,  Y02P70/521

摘要： There is provided a semiconductor wafer including a base wafer that has an impurity region in which an impurity atom has been introduced into silicon, a plurality of seed bodies provided in contact with the impurity region, and a plurality of compound semiconductors each provided in contact with the corresponding seed bodies and lattice-matched or pseudo-lattice-matched to the corresponding seed bodies. The semiconductor wafer can further include an inhibitor provided on the base wafer and in which a plurality of apertures exposing at least a part of the impurity region are provided.

摘要翻译： 提供了一种半导体晶片，其包括：基底晶片，其具有将杂质原子引入到硅中的杂质区域，与杂质区域接触的多个晶种;以及多个化合物半导体，各自与 相应的种子体和与对应的种子晶格匹配或伪晶格匹配。 半导体晶片还可以包括设置在基底晶片上的抑制剂，其中设置暴露至少一部分杂质区域的多个孔。

公开(公告)号：US08878250B2

公开(公告)日：2014-11-04

申请号：US13594442

申请日：2012-08-24

申请人： Masahiko Hata ,  Sadanori Yamanaka ,  Tomoyuki Takada ,  Kazuhiko Honjo

发明人： Masahiko Hata ,  Sadanori Yamanaka ,  Tomoyuki Takada ,  Kazuhiko Honjo

IPC分类号： H01L29/737 ,  H01L23/31 ,  H01L27/06 ,  H01L23/00

CPC分类号： H01L27/0605 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/13023 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element.

摘要翻译： 提供电子器件，其包括：其表面由硅晶体制成的基底晶片; 在硅晶体的部分区域上直接或间接形成的3-5族化合物半导体晶体; 包含部分3-5族化合物半导体晶体作为活性层的电子元件; 直接或间接地形成在基底晶片上并覆盖电子元件的绝缘膜; 在绝缘膜上直接或间接形成的电极; 延伸穿过所述绝缘膜的第一耦合布线，其至少一部分直接或间接地形成在所述绝缘膜上，并且将所述电子元件与所述电极电耦合; 绝缘膜上直接或间接形成的无源元件; 延伸穿过绝缘膜的第二耦合布线，其至少一部分直接或间接地形成在绝缘膜上，并将电子元件与无源元件电连接。

公开(公告)号：US08772830B2

公开(公告)日：2014-07-08

申请号：US12811074

申请日：2008-12-26

申请人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata

发明人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata

IPC分类号： H01L29/12

CPC分类号： H01L29/045 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02516 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/205 ,  H01L29/66242 ,  H01L29/7371

摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be formed then annealing with a temperature and duration that enables movement of crystal defects.

摘要翻译： 实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。 提供了包括Si晶片的半导体晶片; 所述抑制层形成在所述晶片上并且抑制晶体生长，所述抑制层包括覆盖所述晶片的一部分的覆盖区域和不覆盖所述覆盖区域内的所述晶片的一部分的开放区域; 在开放区域晶体生长的Ge层; 在Ge层上晶体生长并且是含有P的3-5族化合物半导体层的缓冲层; 以及在缓冲层上晶体生长的功能层。 可以形成Ge层，然后以能够移动晶体缺陷的温度和持续时间进行退火。

公开(公告)号：US08766318B2

公开(公告)日：2014-07-01

申请号：US12920455

申请日：2009-02-27

申请人： Masahiko Hata ,  Tomoyuki Takada

发明人： Masahiko Hata ,  Tomoyuki Takada

IPC分类号： H01L29/12

CPC分类号： H01L29/16 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02551 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78648 ,  H01L29/78681

摘要： The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that has an open portion reaching the silicon wafer; a Ge crystal formed in the open portion; a seed compound semiconductor crystal that is grown with the Ge crystal as a nucleus and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface.

摘要翻译： 目的是提高复合半导体器件的高速切换等能力。 提供了包括硅晶片的半导体晶片; 绝缘膜，其形成在所述硅晶片上，并且具有到达所述硅晶片的开口部分; 形成在开口部的Ge晶体; 种子化合物半导体晶体，其以Ge晶体为核生长并突出超过绝缘膜的表面; 横向生长的化合物半导体层，其以种子化合物半导体晶体的指定表面作为种子表面在绝缘膜上横向生长。

公开(公告)号：US08709904B2

公开(公告)日：2014-04-29

申请号：US13131523

申请日：2009-11-26

申请人： Tomoyuki Takada ,  Masahiko Hata ,  Hisashi Yamada

发明人： Tomoyuki Takada ,  Masahiko Hata ,  Hisashi Yamada

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/46 ,  H01L21/78 ,  H01L21/26

CPC分类号： H01L21/02532 ,  H01L21/02667 ,  H01L21/2686 ,  H01L21/67115 ,  H01L29/78

摘要： There is provided a method of producing a semiconductor wafer by thermally processing a base wafer having a portion to be thermally processed that is to be thermally processed. The method comprises a step of providing, on the base wafer, a portion to be heated that generates heat through absorption of an electromagnetic wave and selectively heats the portion to be thermally processed, a step of applying an electromagnetic wave to the base wafer, and a step of lowering the lattice defect density of the portion to be thermally processed, by means of the heat generated by the portion to be heated through the absorption of the electromagnetic wave.

摘要翻译： 提供了通过热处理具有待热处理部分的基底晶片来制造半导体晶片的方法。 该方法包括在基底晶片上提供通过吸收电磁波产生热并选择性地加热待热处理的部分的加热部分，向基底晶片施加电磁波的步骤，以及 借助于通过吸收电磁波而被加热部分产生的热量来降低待热处理部分的晶格缺陷密度的步骤。

公开(公告)号：US20110266595A1

公开(公告)日：2011-11-03

申请号：US13122124

申请日：2009-10-01

申请人： Masahiko Hata

发明人： Masahiko Hata

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L21/8252 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02551 ,  H01L21/02645 ,  H01L21/02647 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/20 ,  H01L29/66742 ,  H01L29/7371 ,  H01L29/78681

摘要： There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. The semiconductor wafer further includes an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer. The inhibition layer inhibiting crystal growth of a compound semiconductor. Furthermore, a seed crystal is provided within the opening, and a compound semiconductor has a lattice match or a pseudo lattice match with the seed crystal. There is also provided an electronic device includes a substrate, an insulating layer that is provided on the substrate, a Si crystal layer that is provided on the insulating layer, an inhibition layer that is provided on the Si crystal layer and has an opening penetrating therethrough to reach the Si crystal layer, where the inhibition layer inhibits crystal growth of a compound semiconductor, a seed crystal that is provided within the opening, a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal, and a semiconductor device that is formed using the compound semiconductor.

摘要翻译： 提供了以所述顺序包括基底晶片，绝缘层和Si晶体层的半导体晶片。 半导体晶片还包括设置在Si晶体层上并具有贯穿其的开口以到达Si晶体层的抑制层。 抑制层抑制化合物半导体的晶体生长。 此外，在开口内设置晶种，化合物半导体与晶种具有晶格匹配或伪晶格匹配。 还提供了一种电子器件，包括衬底，设置在衬底上的绝缘层，设置在绝缘层上的Si晶体层，设置在Si晶体层上并具有贯穿其的开口的抑制层 到达Si晶体层，其中抑制层抑制化合物半导体的晶体生长，设置在开口内的晶种，具有晶格匹配或与晶种的伪晶格匹配的化合物半导体以及半导体 使用化合物半导体形成的器件。

公开(公告)号：US20110233689A1

公开(公告)日：2011-09-29

申请号：US13133092

申请日：2009-11-27

申请人： Masahiko Hata ,  Noboru Fukuhara ,  Hisashi Yamada ,  Shinichi Takagi ,  Masakazu Sugiyama ,  Mitsuru Takenaka ,  Tetsuji Yasuda ,  Noriyuki Miyata ,  Taro Itatani ,  Hiroyuki Ishii ,  Akihiro Ohtake ,  Jun Nara

发明人： Masahiko Hata ,  Noboru Fukuhara ,  Hisashi Yamada ,  Shinichi Takagi ,  Masakazu Sugiyama ,  Mitsuru Takenaka ,  Tetsuji Yasuda ,  Noriyuki Miyata ,  Taro Itatani ,  Hiroyuki Ishii ,  Akihiro Ohtake ,  Jun Nara

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/336 ,  H01L29/20 ,  H01L21/20

CPC分类号： H01L29/045 ,  H01L29/20 ,  H01L29/7833 ,  H01L29/78681

摘要： There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.

摘要翻译： 提供了一种半导体器件，其包括具有锌闪光体型晶体结构的III-V族化合物半导体，与III-V族化合物半导体的（111）面接触的绝缘材料， 相当于（111）面的III-V族化合物半导体，或相对于（111）面或与（111）面相当的面的偏角的平面，和与MIS接触的MIS型电极 具有绝缘材料并且包括金属导电材料。

公开(公告)号：US20110227199A1

公开(公告)日：2011-09-22

申请号：US13131513

申请日：2009-11-26

申请人： Masahiko Hata ,  Tomoyuki Takada ,  Hisashi Yamada

发明人： Masahiko Hata ,  Tomoyuki Takada ,  Hisashi Yamada

IPC分类号： H01L29/02 ,  H01L21/20 ,  H05B6/10

CPC分类号： H01L21/8258 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02667 ,  H01L21/2686 ,  H01L21/67115 ,  H01L21/84

摘要： There is provided a method of producing a semiconductor wafer by thermally processing a base wafer having a portion to be thermally processed that has a single-crystal layer and is to be subjected to thermal processing and a portion to be protected that is to be protected from heal, to be added during the thermal processing. The method comprises a step of forming, above the portion to be protected, a protective layer for protecting the portion to be protected from an electromagnetic wave to be applied to the base wafer, and a step of annealing the portion to be thermally processed, by applying the electromagnetic wave to the entire base wafer.

摘要翻译： 提供了一种制造半导体晶片的方法，该方法通过热处理具有单晶层的热处理部分的基底晶片，并进行热处理和被保护的部分， 在热处理过程中加入。 该方法包括在待保护部分上形成用于保护被保护部分免受施加到基底晶片的电磁波的保护层的步骤，以及将要热处理的部分退火的步骤，通过 将电磁波施加到整个基底晶片。