利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

32 条记录 (耗时 0.018 秒)

    Counter/timer array for generation of complex patterns independent of software control
    1.
    发明授权
    Counter/timer array for generation of complex patterns independent of software control 有权

    公开(公告)号：US10416703B2

    公开(公告)日：2019-09-17

    申请号：US15674242

    申请日：2017-08-10

    申请人： Ambiq Micro, Inc.

    发明人： Stephen James Sheafor ,  Donovan Scott Popps

    IPC分类号： G06F1/08 ,  G06F13/42 ,  G06F1/12

    摘要： A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.

    SRAM with Error Correction in Retention Mode
    2.
    发明申请
    SRAM with Error Correction in Retention Mode 审中-公开

    公开(公告)号：US20190074056A1

    公开(公告)日：2019-03-07

    申请号：US15982835

    申请日：2018-05-17

    申请人： Ambiq Micro, Inc.

    发明人： Christophe J. Chevallier ,  Stephen James Sheafor

    IPC分类号： G11C11/412 ,  G11C16/34 ,  G11C15/04 ,  G11C11/56

    摘要： A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

    Very Low Power Microcontroller System
    8.
    发明申请
    Very Low Power Microcontroller System 审中-公开

    公开(公告)号：US20190079573A1

    公开(公告)日：2019-03-14

    申请号：US15933153

    申请日：2018-03-22

    申请人： Ambiq Micro, Inc.

    发明人： Scott McLean Hanson ,  Daniel Martin Cermak ,  Eric Jonathan Deal ,  Stephen James Sheafor ,  Donovan Scott Popps ,  Mark A. Baur

    IPC分类号： G06F1/32

    摘要： A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.