公开(公告)号：US06440750B1

公开(公告)日：2002-08-27

申请号：US09511343

申请日：2000-02-23

申请人： Anatoly Feygenson ,  Dean P. Kossives ,  Ashraf W. Lotfi ,  Lynn F. Schneemeyer ,  Michael L. Steigerwald ,  R. Bruce Van Dover

发明人： Anatoly Feygenson ,  Dean P. Kossives ,  Ashraf W. Lotfi ,  Lynn F. Schneemeyer ,  Michael L. Steigerwald ,  R. Bruce Van Dover

IPC分类号： H01L2100

CPC分类号： H01L23/645 ,  H01F17/0006 ,  H01F41/046 ,  H01L23/5227 ,  H01L27/016 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T428/24917 ,  Y10T428/31681 ,  Y10T428/325 ,  H01L2924/00

摘要： A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

摘要翻译： 一种集成电路的制造方法和采用该集成电路的集成电路。 在一个实施例中，制造集成电路的方法包括（1）保形地映射包括铁磁芯的微磁性装置，以确定其适当的尺寸，（2）在耦合到集成电路的基板的绝缘体上沉积粘合剂，以及 （3）在粘合剂上形成适当尺寸的铁磁芯。

公开(公告)号：US06696744B2

公开(公告)日：2004-02-24

申请号：US09978871

申请日：2001-10-15

申请人： Anatoly Feygenson ,  Dean P. Kossives ,  Ashraf W. Lotfi ,  Lynn F. Schneemeyer ,  Michael L. Steigerwald ,  R. Bruce Van Dover

发明人： Anatoly Feygenson ,  Dean P. Kossives ,  Ashraf W. Lotfi ,  Lynn F. Schneemeyer ,  Michael L. Steigerwald ,  R. Bruce Van Dover

IPC分类号： H01L2940

CPC分类号： H01L23/645 ,  H01F17/0006 ,  H01F41/046 ,  H01L23/5227 ,  H01L27/016 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  Y10T428/24917 ,  Y10T428/31681 ,  Y10T428/325 ,  H01L2924/00

摘要： A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

摘要翻译： 一种集成电路的制造方法和采用该集成电路的集成电路。 在一个实施例中，制造集成电路的方法包括（1）保形地映射包括铁磁芯的微磁性装置，以确定其适当的尺寸，（2）在耦合到集成电路的基板的绝缘体上沉积粘合剂，以及 （3）在粘合剂上形成适当尺寸的铁磁芯。

公开(公告)号：US4860085A

公开(公告)日：1989-08-22

申请号：US238990

申请日：1988-08-24

申请人： Anatoly Feygenson

发明人： Anatoly Feygenson

IPC分类号： H01L29/423 ,  H01L29/732

CPC分类号： H01L29/42304 ,  H01L29/7322 ,  Y10S257/90

摘要： A high performance bipolar transistor structure is disclosed which exhibits an extremely low extrinsic base resistance by virtue of a silicide layer which is included in the base contact portion of the structure. The silicide layer is situated to be electrically in parallel with the conventional heavily-doped polysilicon base contact region, where a vertical polysilicon runner is used to provide a self-aligned electrical contact to the base. The parallel combination of the low resistivity (0.5-4 ohm/square) silicide with the polysilicon (sheet resistance of 10-100 ohm/square) results in a low extrinsic base resistance on the order of 0.5-4 ohm/square. The disclosed device also includes a submicron emitter size, defined by vertical oxide sidewalls above the base region, which further improves the high frequency performance of the device.

摘要翻译： 公开了一种高性能双极晶体管结构，其通过包含在该结构的基极接触部分中的硅化物层，显示出极低的外在基极电阻。 硅化物层被定位成与传统的重掺杂多晶硅基底接触区域电并联，其中使用垂直多晶硅流道来提供与基底的自对准电接触。 低电阻率（0.5-4欧姆/平方）的硅化物与多晶硅（薄层电阻为10-100欧姆/平方）的并联组合导致0.5-4欧姆/平方的低的外在基极电阻。 所公开的器件还包括由基极区域上方的垂直氧化物侧壁限定的亚微米发射极尺寸，这进一步提高了器件的高频性能。

公开(公告)号：US09870925B1

公开(公告)日：2018-01-16

申请号：US13964192

申请日：2013-08-12

申请人： Anatoly Feygenson

发明人： Anatoly Feygenson

IPC分类号： H01L21/20 ,  H01L21/36 ,  H01L21/223 ,  H01L29/36 ,  H01L21/225 ,  H01L29/15 ,  H01L21/67 ,  H01L21/02 ,  H01L29/8605 ,  H01L29/772 ,  H01L21/3215 ,  H01L21/203 ,  H01L29/66

CPC分类号： H01L29/7725 ,  H01L21/02 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02557 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/203 ,  H01L21/2254 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67167 ,  H01L21/67207 ,  H01L29/0847 ,  H01L29/122 ,  H01L29/155 ,  H01L29/157 ,  H01L29/1606 ,  H01L29/365 ,  H01L29/66 ,  H01L29/7782 ,  H01L29/8605

摘要： A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.

公开(公告)号：US5747982A

公开(公告)日：1998-05-05

申请号：US761047

申请日：1996-12-05

申请人： Douglas John Dromgoole ,  Anatoly Feygenson ,  Robert Charles Frye ,  Ashraf Wagih Lotfi ,  King Lien Tai

发明人： Douglas John Dromgoole ,  Anatoly Feygenson ,  Robert Charles Frye ,  Ashraf Wagih Lotfi ,  King Lien Tai

IPC分类号： H01L25/16 ,  H05K1/02 ,  G05F5/00 ,  H03H7/00

CPC分类号： H05K1/0256 ,  H01L25/162 ,  H05K1/0262 ,  H05K1/0274 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/1003 ,  Y10S323/902

摘要： A silicon-on-silicon dual MCM apparatus comprising a printed circuit board having a voltage isolation boundary contained therein supporting a pair of multi-chip modules on either side of the voltage isolation boundary. The MCMs safely convey signals across the isolation boundary via discrete optical coupling means or the like. The optical coupling means allow safe and efficient conveyance of signals across the voltage isolation boundary enabling a designer to group high voltage components on one side of the boundary and low voltage components on the other side of the boundary. This obviates to a degree the need for multi-layered PCBs. A relatively large number of passive components (resistors and capacitors) are integrated into a silicon substrate with flip-chip analog integrated circuits (ICs). Operational characteristics of the controller are verified after integration and are compared to the discrete version. High voltage isolation requirements, interference, and noise are all considered to determine the most critical portions of the dual MCM layout and design.

摘要翻译： 一种硅上硅双MCM装置，包括其中包含电压隔离边界的印刷电路板，其在电压隔离边界的两侧支撑一对多芯片模块。 MCM通过离散光耦合装置等将信号安全地传送到隔离边界。 光耦合装置允许跨越电压隔离边界安全有效地传输信号，使得设计人员可以对边界一侧的高压部件和边界另一侧的低电压部件进行分组。 这在一定程度上消除了对多层PCB的需求。 通过倒装芯片模拟集成电路（IC）将相对大量的无源元件（电阻和电容器）集成到硅衬底中。 控制器的操作特性在集成后验证，并与离散版本进行比较。 高电压隔离要求，干扰和噪声都被认为是确定双MCM布局和设计的最关键部分。

公开(公告)号：US20180174842A1

公开(公告)日：2018-06-21

申请号：US15834610

申请日：2017-12-07

申请人： Anatoly Feygenson

发明人： Anatoly Feygenson

IPC分类号： H01L21/223 ,  H01L29/36 ,  H01L21/02 ,  H01L29/66 ,  H01L29/15 ,  H01L21/67 ,  H01L21/3215 ,  H01L21/225 ,  H01L21/203 ,  H01L29/8605 ,  H01L29/772

CPC分类号： H01L29/7725 ,  H01L21/02 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02557 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/203 ,  H01L21/2254 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67167 ,  H01L21/67207 ,  H01L29/0847 ,  H01L29/122 ,  H01L29/155 ,  H01L29/157 ,  H01L29/1606 ,  H01L29/365 ,  H01L29/66 ,  H01L29/7782 ,  H01L29/8605

摘要： A novel doping technology for semiconductor wafers has been developed, referred to as a “quantum doping” process that permits the deposition of only a fixed, controlled number of atoms in the form of a monolayer in a substitutional condition where only unterminated surface bonds react with the dopant, thus depositing only a number of atoms equal to the atomic surface density of the substrate material. This technique results in providing a “quantized” set of possible dopant concentration values that depend only on the additional number of layers of substrate material formed over the single layer of dopant atoms.

公开(公告)号：US4987471A

公开(公告)日：1991-01-22

申请号：US528273

申请日：1990-05-21

申请人： William G. Easter ,  Anatoly Feygenson

发明人： William G. Easter ,  Anatoly Feygenson

IPC分类号： H01L21/225 ,  H01L21/74 ,  H01L21/762

CPC分类号： H01L21/76297 ,  H01L21/2257 ,  H01L21/74

摘要： A dielectrically-isolated structure and method of fabricating the same is disclosed wherein the structure includes a layer of silicide which is selectively doped, preferably using an ion implantation process. The doped silicide is then used as the diffusion source for the subsequent formation (through a heat treatment) of various active portions (collector, emitter, drain, source, for example) of a variety of high-voltage, high-speed active devices. The non-doped silicide is advantageously utilized as a low-resistance contact between the buried diffusion region and the surface electrode.

摘要翻译： 公开了一种介电隔离结构及其制造方法，其中该结构包括选择性掺杂的硅化物层，优选使用离子注入工艺。 然后将掺杂的硅化物用作扩散源，用于随后通过各种高电压，高速有源器件的各种有源部分（例如集电极，发射极，漏极，源极）的形成（通过热处理）。 非掺杂硅化物有利地用作掩埋扩散区和表面电极之间的低电阻接触。

公开(公告)号：US4818713A

公开(公告)日：1989-04-04

申请号：US111002

申请日：1987-10-20

申请人： Anatoly Feygenson

发明人： Anatoly Feygenson

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/331 ,  H01L21/205 ,  H01L21/265 ,  H01L21/76

CPC分类号： H01L21/033 ,  Y10S148/01 ,  Y10S148/117 ,  Y10S438/947

摘要： Submicron resolution in the fabrication of transistors is obtained by using sidewall techniques. The techniques described remove the sidewalls after oxidizing the materials between the sidewalls and the openings so formed by the removal are used as a mask for subsequent substrate modification by either diffusion or ion implantation.

公开(公告)号：US4651410A

公开(公告)日：1987-03-24

申请号：US683152

申请日：1984-12-18

申请人： Anatoly Feygenson

发明人： Anatoly Feygenson

IPC分类号： H01L21/20 ,  H01L21/331 ,  H01L21/8228 ,  H01L29/73 ,  H01L29/732 ,  H01L21/477

CPC分类号： H01L29/66287 ,  H01L21/2022 ,  H01L21/82285 ,  H01L29/7317 ,  H01L29/732

摘要： A method of fabricating bipolar integratable transistors includes a recrystallization step. A monocrystalline epitaxial layer is deposited upon a highly doped substrate and impurities are introduced into a portion of the epitaxial layer to form a first transistor region. A polysilicon layer is deposited upon the surface and a portion of the polycrystalline layer is recrystallized wherein the first transistor region serves as a seed. Impurities are introduced into the recrystallized portion to form a base. An additional polysilicon layer is deposited over the substrate and a portion is recrystallized wherein the base serves as a seed. A second transistor region is formed in the recrystallized portion of the additional polysilicon layer.

摘要翻译： 制造双极可积分晶体管的方法包括重结晶步骤。 将单晶外延层沉积在高度掺杂的衬底上，并将杂质引入到外延层的一部分中以形成第一晶体管区域。 在表面上沉积多晶硅层，并且多晶层的一部分被重结晶，其中第一晶体管区域用作晶种。 将杂质引入重结晶部分以形成碱。 在衬底上沉积另外的多晶硅层，并且将部分重结晶，其中碱用作种子。 在附加多晶硅层的再结晶部分中形成第二晶体管区域。

公开(公告)号：US20050154600A1

公开(公告)日：2005-07-14

申请号：US10753270

申请日：2004-01-08

申请人： Anatoly Feygenson ,  Mark Popolano

发明人： Anatoly Feygenson ,  Mark Popolano

IPC分类号： G06Q10/00 ,  G06F17/60

CPC分类号： G06Q10/10 ,  G06Q10/063112 ,  G06Q10/1053

摘要： An extended work program (EWP) is provided in which unemployed and under-employed workers perform atomic units of work. The inventive system and method includes an administrative system, employer systems and participant systems, each of which communicates over the Internet. Employers locate EWP participants by querying an administrative system, which provides information regarding a pool of participants and further announces the available work to the pool. After suitable candidates are located, the administrative system, in conjunction with the employers' systems, trains, evaluates, and compensates EWP participants on an atomic unit of work basis. The participants communicate, in a human-centric trusted computing environment, with the employers through the administrative system.

摘要翻译： 提供了一个扩大的工作方案（EWP），失业和就业不足的工人执行原子工作单位。 本发明的系统和方法包括管理系统，雇主系统和参与者系统，每个系统和参与者系统通过因特网进行通信。 雇主通过查询管理系统来查找EWP参与者，该管理系统提供有关参与者池的信息，并进一步向池中宣布可用的工作。 在适当的候选人找到之后，行政系统与雇主制度一起，以原子工单为基础对EWP参与者进行培训，评估和补偿。 参与者以人为中心的可信计算环境通过行政系统与雇主进行沟通。