公开(公告)号：US08410599B2

公开(公告)日：2013-04-02

申请号：US12756915

申请日：2010-04-08

申请人： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

发明人： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

IPC分类号： H01L23/04

CPC分类号： H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

摘要翻译： 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US20100289092A1

公开(公告)日：2010-11-18

申请号：US12756915

申请日：2010-04-08

申请人： Baw-Ching PERNG ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

发明人： Baw-Ching PERNG ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Jui Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

IPC分类号： H01L29/78 ,  H01L23/538

CPC分类号： H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

摘要翻译： 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US08541877B2

公开(公告)日：2013-09-24

申请号：US12849089

申请日：2010-08-03

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC分类号： H01L23/48

CPC分类号： H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

摘要翻译： 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US20110140267A1

公开(公告)日：2011-06-16

申请号：US12849089

申请日：2010-08-03

申请人： Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

发明人： Chia-Lun TSAI ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

摘要： The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

摘要翻译： 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US07968448B2

公开(公告)日：2011-06-28

申请号：US12466656

申请日：2009-05-15

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

摘要翻译： 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US20090283877A1

公开(公告)日：2009-11-19

申请号：US12466656

申请日：2009-05-15

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC分类号： H01L23/552 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

摘要翻译： 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US08431950B2

公开(公告)日：2013-04-30

申请号：US12471255

申请日：2009-05-22

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/385 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

摘要翻译： 描述了发光器件封装结构。 发光器件封装结构包括用作支撑发光器件芯片的载体的衬底。 基板和发光元件芯片分别具有芯片侧和基板侧。 第一电极层设置在发光器件芯片的第一表面上，并且第二电极层设置在发光器件芯片的第二表面上，其中第一表面和第二表面不是共面的。 第一导电迹线电连接到第一电极层，并且第二导电迹线电连接到第二电极层。 至少第一导电迹线或第二导电迹线同时沿着芯片侧和衬底侧形成。

公开(公告)号：US20110140248A1

公开(公告)日：2011-06-16

申请号：US13030887

申请日：2011-02-18

申请人： Chia-Lun TSAI ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

发明人： Chia-Lun TSAI ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC分类号： H01L23/552 ,  H01L23/485

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

摘要翻译： 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US08384222B2

公开(公告)日：2013-02-26

申请号：US13030887

申请日：2011-02-18

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Jack Chen ,  Wen-Cheng Chien

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor device and manufacturing method thereof are disclosed. The device comprises a semiconductor die, a passivation layer, a wiring redistribution layer (RDL), an Ni/Au layer, and a solder mask. The semiconductor die comprises a top metal exposed in an active surface thereof. The passivation layer overlies the active surface of the semiconductor die, and comprises a through passivation opening overlying the top metal. The wiring RDL, comprising an Al layer, overlies the passivation layer, and electrically connects to the top metal via the passivation opening. The solder mask overlies the passivation layer and the wiring RDL, exposing a terminal of the wiring RDL.

摘要翻译： 公开了一种半导体器件及其制造方法。 该器件包括半导体管芯，钝化层，布线再分布层（RDL），Ni / Au层和焊料掩模。 半导体管芯包括在其活性表面中暴露的顶部金属。 钝化层覆盖半导体管芯的有源表面，并且包括覆盖顶部金属的贯通钝化开口。 包括Al层的布线RDL覆盖钝化层，并通过钝化开口电连接到顶部金属。 焊接掩模覆盖钝化层和布线RDL，露出布线RDL的端子。

公开(公告)号：US20090289273A1

公开(公告)日：2009-11-26

申请号：US12471255

申请日：2009-05-22

申请人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

发明人： Chia-Lun Tsai ,  Ching-Yu Ni ,  Wen-Cheng Chien ,  Shang-Yi Wu ,  Cheng-Te Chou

IPC分类号： H01L33/00

CPC分类号： H01L33/385 ,  H01L33/62 ,  H01L33/64 ,  H01L33/642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A light emitting device package structure is described. The light emitting device package structure includes a substrate serving as a carrier supporting a light emitting device chip. The substrate and the light emitting device chip have a chip side and a substrate side separately. A first electrode layer is disposed on a first surface of the light emitting device chip and a second electrode layer is disposed on a second surface of the light emitting device chip, in which the first surface and the second surface are not coplanar. A first conductive trace is electrically connected to the first electrode layer and a second conductive trace is electrically connected to the second electrode layer. At least the first conductive trace or the second conductive trace is formed along the chip side and the substrate side simultaneously.

摘要翻译： 描述了发光器件封装结构。 发光器件封装结构包括用作支撑发光器件芯片的载体的衬底。 基板和发光元件芯片分别具有芯片侧和基板侧。 第一电极层设置在发光器件芯片的第一表面上，并且第二电极层设置在发光器件芯片的第二表面上，其中第一表面和第二表面不是共面的。 第一导电迹线电连接到第一电极层，并且第二导电迹线电连接到第二电极层。 至少第一导电迹线或第二导电迹线同时沿着芯片侧和衬底侧形成。