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公开(公告)号：US08410599B2
公开(公告)日：2013-04-02
申请号：US12756915
申请日：2010-04-08
申请人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
发明人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
IPC分类号： H01L23/04
CPC分类号： H01L29/78 , H01L23/3114 , H01L23/481 , H01L23/492 , H01L24/13 , H01L24/16 , H01L29/0646 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/7802 , H01L29/7809 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/01021 , H01L2924/13091 , H01L2224/05599 , H01L2224/05099
摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.
摘要翻译： 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。
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公开(公告)号：US20100289092A1
公开(公告)日：2010-11-18
申请号：US12756915
申请日：2010-04-08
申请人： Baw-Ching PERNG , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
发明人： Baw-Ching PERNG , Ying-Nan Wen , Shu-Ming Chang , Ching-Yu Ni , Yun-Jui Hsieh , Wei-Ming Chen , Chia-Lun Tsai , Chia-Ming Cheng
IPC分类号： H01L29/78 , H01L23/538
CPC分类号： H01L29/78 , H01L23/3114 , H01L23/481 , H01L23/492 , H01L24/13 , H01L24/16 , H01L29/0646 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/7802 , H01L29/7809 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05572 , H01L2224/16 , H01L2924/00014 , H01L2924/01021 , H01L2924/13091 , H01L2224/05599 , H01L2224/05099
摘要： A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.
摘要翻译： 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。
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公开(公告)号：US08564133B2
公开(公告)日：2013-10-22
申请号：US12860823
申请日：2010-08-20
申请人： Ying-Nan Wen , Baw-Ching Perng , Wei-Ming Chen , Shu-Ming Chang
发明人： Ying-Nan Wen , Baw-Ching Perng , Wei-Ming Chen , Shu-Ming Chang
IPC分类号： H01L23/52
CPC分类号： H01L23/3135 , H01L21/76898 , H01L23/147 , H01L23/3121 , H01L23/481 , H01L23/49827 , H01L24/16 , H01L24/24 , H01L24/28 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/16225 , H01L2224/24051 , H01L2224/24226 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/8314 , H01L2224/8385 , H01L2224/92 , H01L2224/92244 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/078 , H01L2924/07802 , H01L2924/12041 , H01L2924/12044 , H01L2924/1461 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes a semiconductor substrate having an upper surface and an opposite lower surface, a through-hole penetrating the upper surface and the lower surface of the semiconductor substrate, a chip disposed overlying the upper surface of the semiconductor substrate, a conducting layer overlying a sidewall of the through-hole and electrically connecting the chip, a first insulating layer overlying the upper surface of the semiconductor substrate, a second insulating layer overlying the lower surface of the semiconductor substrate, and a bonding structure disposed overlying the lower surface of the semiconductor substrate, wherein a material of the second insulating layer is different from that of the first insulating layer.
摘要翻译： 根据本发明的实施例，提供了一种芯片封装。 芯片封装包括具有上表面和相对的下表面的半导体衬底，穿过半导体衬底的上表面和下表面的通孔，设置在半导体衬底的上表面上的芯片，覆盖 所述通孔的侧壁电连接所述芯片，覆盖所述半导体衬底的上表面的第一绝缘层，覆盖所述半导体衬底的下表面的第二绝缘层和设置在所述半导体衬底的下表面上的接合结构 半导体衬底，其中所述第二绝缘层的材料与所述第一绝缘层的材料不同。
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公开(公告)号：US08610271B2
公开(公告)日：2013-12-17
申请号：US12957159
申请日：2010-11-30
申请人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang
发明人： Baw-Ching Perng , Ying-Nan Wen , Shu-Ming Chang
CPC分类号： H01L25/50 , B81B2207/012 , B81B2207/07 , B81B2207/098 , B81C1/0023 , B81C2203/0109 , B81C2203/0792 , H01L21/6835 , H01L24/94 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2924/01006 , H01L2924/01013 , H01L2924/01021 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16235 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.
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公开(公告)号：US20110127670A1
公开(公告)日：2011-06-02
申请号：US12957159
申请日：2010-11-30
申请人： Baw-Ching PERNG , Ying-Nan Wen , Shu-Ming Chang
发明人： Baw-Ching PERNG , Ying-Nan Wen , Shu-Ming Chang
CPC分类号： H01L25/50 , B81B2207/012 , B81B2207/07 , B81B2207/098 , B81C1/0023 , B81C2203/0109 , B81C2203/0792 , H01L21/6835 , H01L24/94 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2924/01006 , H01L2924/01013 , H01L2924/01021 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16235 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.
摘要翻译： 芯片封装包括具有上表面和下表面的衬底，并且包括：至少第一接触焊盘; 设置在上表面上的非光学传感器芯片，其中所述非光学传感器芯片至少包括第二接触焊盘并具有第一长度; 设置在所述非光学传感器芯片上的保护盖，其中所述保护盖具有第二长度，所述第二长度的延伸方向基本上平行于所述第一长度的延伸方向，并且所述第二长度短于所述第一长度; 设置在所述保护盖上的IC芯片，其中所述IC芯片包括至少第三接触焊盘并具有第三长度，并且所述第三长度的延伸方向基本上与所述第一长度的延伸方向平行; 以及在基板，非光学传感器芯片和IC芯片之间形成电连接的接合线。
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公开(公告)号：US08823179B2
公开(公告)日：2014-09-02
申请号：US12667383
申请日：2008-06-13
申请人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
发明人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
IPC分类号： H01L23/48 , H01L27/146 , H01L21/768 , H01L23/00
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05655 , H01L2924/00014 , H01L2924/01021 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要： An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.
摘要翻译： 本发明的实施例提供了一种电子器件封装，其包括具有第一表面和相对的第二表面的芯片以及沿着从第二表面到第一表面的方向延伸到芯片的主体中的沟槽，其中底部 沟槽的一部分包括至少两个接触孔。
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公开(公告)号：US20100187697A1
公开(公告)日：2010-07-29
申请号：US12667383
申请日：2008-06-13
申请人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
发明人： Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
IPC分类号： H01L23/528
CPC分类号： H01L23/481 , H01L21/76898 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05655 , H01L2924/00014 , H01L2924/01021 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要： An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.
摘要翻译： 本发明的实施例提供了一种电子器件封装，其包括具有第一表面和相对的第二表面的芯片以及沿着从第二表面到第一表面的方向延伸到芯片的主体中的沟槽，其中底部 沟槽的一部分包括至少两个接触孔。
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公开(公告)号：US08710680B2
公开(公告)日：2014-04-29
申请号：US13052769
申请日：2011-03-21
申请人： Shu-Ming Chang , Bai-Yao Lou , Ying-Nan Wen , Chien-Hung Liu
发明人： Shu-Ming Chang , Bai-Yao Lou , Ying-Nan Wen , Chien-Hung Liu
IPC分类号： H01L29/40
CPC分类号： H01L21/50 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/32 , H01L24/81 , H01L24/92 , H01L24/93 , H01L24/94 , H01L33/62 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/02371 , H01L2224/0239 , H01L2224/024 , H01L2224/0346 , H01L2224/0347 , H01L2224/03825 , H01L2224/039 , H01L2224/0391 , H01L2224/0401 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/1146 , H01L2224/1147 , H01L2224/11825 , H01L2224/119 , H01L2224/1191 , H01L2224/13021 , H01L2224/13024 , H01L2224/131 , H01L2224/136 , H01L2224/16225 , H01L2224/32052 , H01L2224/32225 , H01L2224/32245 , H01L2224/81191 , H01L2224/81192 , H01L2224/92142 , H01L2224/92143 , H01L2224/93 , H01L2224/94 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2224/0231 , H01L2224/11 , H01L2224/1182 , H01L2224/03 , H01L2224/0382 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要： An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.
摘要翻译： 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。
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公开(公告)号：US08614488B2
公开(公告)日：2013-12-24
申请号：US13314114
申请日：2011-12-07
申请人： Ying-Nan Wen , Ho-Yin Yiu , Yen-Shih Ho , Shu-Ming Chang , Chien-Hung Liu , Shih-Yi Lee , Wei-Chung Yang
发明人： Ying-Nan Wen , Ho-Yin Yiu , Yen-Shih Ho , Shu-Ming Chang , Chien-Hung Liu , Shih-Yi Lee , Wei-Chung Yang
IPC分类号： H01L21/70
CPC分类号： H01L21/76898 , H01L21/6835 , H01L23/3114 , H01L23/3185 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68363 , H01L2224/02372 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05669 , H01L2224/05672 , H01L2224/11002 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2924/00013 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.
摘要翻译： 芯片封装包括：基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构，源极导电结构和栅极导电结构，分别设置在所述衬底上并电连接到所述漏极区域，所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域，其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构，其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极，其中所述漏极，所述源极，所述栅极，所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。
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公开(公告)号：US20110233782A1
公开(公告)日：2011-09-29
申请号：US13052769
申请日：2011-03-21
申请人： Shu-Ming CHANG , Bai-Yao Lou , Ying-Nan Wen , Chien-Hung Liu
发明人： Shu-Ming CHANG , Bai-Yao Lou , Ying-Nan Wen , Chien-Hung Liu
CPC分类号： H01L21/50 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/32 , H01L24/81 , H01L24/92 , H01L24/93 , H01L24/94 , H01L33/62 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/02371 , H01L2224/0239 , H01L2224/024 , H01L2224/0346 , H01L2224/0347 , H01L2224/03825 , H01L2224/039 , H01L2224/0391 , H01L2224/0401 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/1146 , H01L2224/1147 , H01L2224/11825 , H01L2224/119 , H01L2224/1191 , H01L2224/13021 , H01L2224/13024 , H01L2224/131 , H01L2224/136 , H01L2224/16225 , H01L2224/32052 , H01L2224/32225 , H01L2224/32245 , H01L2224/81191 , H01L2224/81192 , H01L2224/92142 , H01L2224/92143 , H01L2224/93 , H01L2224/94 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2224/0231 , H01L2224/11 , H01L2224/1182 , H01L2224/03 , H01L2224/0382 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要： An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.
摘要翻译： 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片，其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。
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