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    SILICON NANOWIRE ARRAYS ON AN ORGANIC CONDUCTOR
    2.
    发明申请
    SILICON NANOWIRE ARRAYS ON AN ORGANIC CONDUCTOR 审中-公开
    有机导体上的硅纳米线阵列

    公开(公告)号：US20110024169A1

    公开(公告)日：2011-02-03

    申请号：US12845557

    申请日：2010-07-28

    申请人： Brent A. Buchine ,  Jeff Miller ,  Marcie R. Black ,  Faris Modawar

    发明人： Brent A. Buchine ,  Jeff Miller ,  Marcie R. Black ,  Faris Modawar

    IPC分类号： H05K1/00 ,  C23F1/24 ,  B82Y30/00

    CPC分类号： H01L31/0352 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/605 ,  H01L51/0048 ,  H01L51/0052 ,  H01M4/0492 ,  H01M4/134 ,  H01M4/1395 ,  H01M4/66 ,  H01M10/052 ,  H01M2004/022

    摘要： In an aspect of the invention, a process to make a nanowire array is provided. In the process, silicon is deposited onto a conductive substrate comprising an organic material and optionally a conductive layer, thus forming a silicon-containing layer. Nanoparticles are deposited on top of the silicon-containing layer. Metal is deposited on top of the nanoparticles and silicon in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is contacted with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.

    摘要翻译： 在本发明的一个方面，提供了制备纳米线阵列的方法。 在该过程中，将硅沉积到包含有机材料和任选的导电层的导电基底上，从而形成含硅层。 纳米颗粒沉积在含硅层的顶部。 金属以这样的方式沉积在纳米颗粒和硅的顶部上，使得金属存在并且接触需要蚀刻的硅并且阻止其接触硅或不存在于其中的硅。 金属化衬底与包含约2至约49重量％的HF和氧化剂的蚀刻剂水溶液接触。

    Process for structuring silicon
    4.
    发明授权
    Process for structuring silicon 有权
    硅结构工艺

    公开(公告)号：US08734659B2

    公开(公告)日：2014-05-27

    申请号：US12576490

    申请日：2009-10-09

    申请人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

    发明人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

    IPC分类号： B29D11/00 ,  B44C1/22

    CPC分类号： H01L29/34 ,  B81C1/00619 ,  H01L21/30604

    摘要： A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H2O2, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.

    摘要翻译： 提供了一种用于蚀刻含硅衬底以形成结构的工艺。 在该过程中，将金属沉积并图案化到含硅衬底（通常具有高于1-10欧姆 - 厘米电阻率的衬底），使得金属存在并接触需要蚀刻并被阻挡的硅 触摸硅或其他地方不存在。 将金属化衬底浸入包含约4至约49重量％的HF和氧化剂如约0.5至约30重量％的H 2 O 2的蚀刻剂水溶液中，从而产生具有一个或多个沟槽的金属化衬底。 任选地使用第二硅蚀刻来去除一个或多个沟槽内的纳米线。

    Process for Structuring Silicon
    6.
    发明申请
    Process for Structuring Silicon 有权
    硅结构工艺

    公开(公告)号：US20100092888A1

    公开(公告)日：2010-04-15

    申请号：US12576490

    申请日：2009-10-09

    申请人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

    发明人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

    IPC分类号： G03F7/20 ,  B32B3/10 ,  B32B15/00 ,  C23F1/00 ,  H01L33/00 ,  H01L31/0216

    CPC分类号： H01L29/34 ,  B81C1/00619 ,  H01L21/30604

    摘要： A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent H2O2, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.

    摘要翻译： 提供了一种用于蚀刻含硅衬底以形成结构的工艺。 在该过程中，将金属沉积并图案化到含硅衬底（通常具有高于1-10欧姆 - 厘米电阻率的衬底），使得金属存在并接触需要蚀刻并被阻挡的硅 触摸硅或其他地方不存在。 将金属化衬底浸入包含约4至约49重量％的HF和氧化剂如约0.5至约30重量％的H 2 O 2的蚀刻剂水溶液中，从而产生具有一个或多个沟槽的金属化衬底。 任选地使用第二硅蚀刻来去除一个或多个沟槽内的纳米线。

    Nanostructured devices
    7.
    发明授权
    Nanostructured devices 有权
    纳米结构设备

    公开(公告)号：US08450599B2

    公开(公告)日：2013-05-28

    申请号：US12619092

    申请日：2009-11-16

    申请人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

    发明人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

    IPC分类号： H01L31/00 ,  H01L21/00

    CPC分类号： H01L31/035254 ,  H01L31/02363 ,  H01L31/035227 ,  H01L31/035281 ,  H01L31/068 ,  Y02E10/50

    摘要： A photovoltaic device is provided. It comprises at least two electrical contacts, p type dopants and n type dopants. It also comprises a bulk region and nanowires in an aligned array which contact the bulk region. All nanowires in the array have one predominant type of dopant, n or p, and at least a portion of the bulk region also comprises that predominant type of dopant. The portion of the bulk region comprising the predominant type of dopant typically contacts the nanowire array. The photovoltaic devices' p-n junction would then be found in the bulk region. The photovoltaic devices would commonly comprise silicon.

    摘要翻译： 提供光伏器件。 它包括至少两个电触点，p型掺杂剂和n型掺杂剂。 它还包括接触大块区域的排列阵列中的体区域和纳米线。 阵列中的所有纳米线具有一种主要类型的掺杂剂n或p，并且本体区域的至少一部分还包括该主要类型的掺杂剂。 包含主要类型掺杂剂的体区的部分通常接触纳米线阵列。 光伏器件的p-n结将在大块区域中被发现。 光伏器件通常包括硅。

    Nanostructured Devices
    8.
    发明申请
    Nanostructured Devices 有权
    纳米结构器件

    公开(公告)号：US20100122725A1

    公开(公告)日：2010-05-20

    申请号：US12619092

    申请日：2009-11-16

    申请人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

    发明人： Brent A. Buchine ,  Faris Modawar ,  Marcie R. Black

    IPC分类号： H01L31/0352 ,  H01L31/18 ,  H01L33/00

    CPC分类号： H01L31/035254 ,  H01L31/02363 ,  H01L31/035227 ,  H01L31/035281 ,  H01L31/068 ,  Y02E10/50

    摘要： A photovoltaic device is provided. It comprises at least two electrical contacts, p type dopants and n type dopants. It also comprises a bulk region and nanowires in an aligned array which contact the bulk region. All nanowires in the array have one predominant type of dopant, n or p, and at least a portion of the bulk region also comprises that predominant type of dopant. The portion of the bulk region comprising the predominant type of dopant typically contacts the nanowire array. The photovoltaic devices' p-n junction would then be found in the bulk region. The photovoltaic devices would commonly comprise silicon.

    摘要翻译： 提供光伏器件。 它包括至少两个电触点，p型掺杂剂和n型掺杂剂。 它还包括接触大块区域的排列阵列中的体区域和纳米线。 阵列中的所有纳米线具有一种主要类型的掺杂剂n或p，并且本体区域的至少一部分还包括该主要类型的掺杂剂。 包含主要类型掺杂剂的体区的部分通常接触纳米线阵列。 光伏器件的p-n结将在大块区域中被发现。 光伏器件通常包括硅。

    Selective emitter nanowire array and methods of making same
    10.
    发明授权
    Selective emitter nanowire array and methods of making same 有权
    选择性发射体纳米线阵列及其制作方法

    公开(公告)号：US08829485B2

    公开(公告)日：2014-09-09

    申请号：US13353091

    申请日：2012-01-18

    申请人： Faris Modawar ,  Marcie R. Black ,  Brian Murphy ,  Jeff Miller ,  Mike Jura

    发明人： Faris Modawar ,  Marcie R. Black ,  Brian Murphy ,  Jeff Miller ,  Mike Jura

    IPC分类号： H01L29/06 ,  H01L31/0352

    CPC分类号： H01L31/035227 ,  H01L31/02167 ,  H01L31/028 ,  H01L31/0284 ,  H01L31/0288 ,  H01L31/068 ,  H01L31/1804 ,  H01L31/1868 ,  Y10S977/762

    摘要： Another aspect of the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure including the same material as the substrate having a non-nanostructured surface of a dimension suitable for forming an electrical contact, located on the same side of the substrate as the array of silicon nanowires; wherein the contacting structure is doped with a greater impurity concentration than the nanowire array, thereby forming a selective emitter.

    摘要翻译： 本公开的另一方面涉及包括具有顶表面和底表面的基底的装置; 具有基底和顶表面的纳米线阵列，所述基底接触所述基底的顶表面; 接触结构包括与衬底相同的材料，其具有适于形成电接触的尺寸的非纳米结构化表面，位于与硅纳米线阵列相同的衬底侧; 其中所述接触结构被掺杂有比所述纳米线阵列更大的杂质浓度，由此形成选择性发射极。