公开(公告)号：US09666453B2

公开(公告)日：2017-05-30

申请号：US13546281

申请日：2012-07-11

申请人： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

发明人： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC分类号： H01L21/56 ,  H01L23/498

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/35121

摘要： A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.

公开(公告)号：US20130299968A1

公开(公告)日：2013-11-14

申请号：US13546281

申请日：2012-07-11

申请人： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

发明人： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC分类号： H01L23/498 ,  H01L21/28

CPC分类号： H01L23/49838 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/35121

摘要： A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.

摘要翻译： 提供一种半导体封装，其包括：具有金属图案层的基板; 形成在所述基板上的半导体管芯; 以及填充在基板和半导体管芯之间的底部填充物。 在金属图案层中形成至少一个开口以减小基底上的金属图案层的面积，从而减小底部填充物和金属图案层之间的接触面积，从而消除了底部填充物的分层。

公开(公告)号：US08698326B2

公开(公告)日：2014-04-15

申请号：US11900345

申请日：2007-09-10

申请人： Wen-Home Huang ,  Wen-Tsung Tseng ,  Chang-Fu Lin ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

发明人： Wen-Home Huang ,  Wen-Tsung Tseng ,  Chang-Fu Lin ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/28 ,  H01L23/48

CPC分类号： H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L29/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.

摘要翻译： 公开了半导体封装及其制造方法。 该制造方法包括以下步骤：提供具有与活性表面相对的活性表面和非活性表面的半导体芯片，粗糙化非活性表面的周边部分，以将非活性表面划分成周边部分 形成有粗糙结构和非粗糙化的中心部分，通过形成在有源表面上的多个焊料凸块将半导体芯片安装在芯片载体上，在芯片载体上形成密封剂以封装半导体芯片。 形成在半导体芯片的非活性表面的周边部分上的粗糙结构可以加强半导体芯片和密封剂之间的接合，并且半导体芯片的非活性表面的非粗糙化的中心部分可以保持 半导体芯片的结构强度。

公开(公告)号：US20080061451A1

公开(公告)日：2008-03-13

申请号：US11900345

申请日：2007-09-10

申请人： Wen-Home Huang ,  Wen-Tsung Tseng ,  Chang-Fu Lin ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

发明人： Wen-Home Huang ,  Wen-Tsung Tseng ,  Chang-Fu Lin ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L29/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.

摘要翻译： 公开了半导体封装及其制造方法。 该制造方法包括以下步骤：提供具有与活性表面相对的活性表面和非活性表面的半导体芯片，粗糙化非活性表面的周边部分，以将非活性表面划分成周边部分 形成有粗糙结构和非粗糙化的中心部分，通过形成在有源表面上的多个焊料凸块将半导体芯片安装在芯片载体上，在芯片载体上形成密封剂以封装半导体芯片。 形成在半导体芯片的非活性表面的周边部分上的粗糙结构可以加强半导体芯片和密封剂之间的接合，并且半导体芯片的非活性表面的非粗糙化的中心部分可以保持 半导体芯片的结构强度。

公开(公告)号：US20110287588A1

公开(公告)日：2011-11-24

申请号：US13195639

申请日：2011-08-01

申请人： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

发明人： Wen-Tsung Tseng ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/56

CPC分类号： H01L23/4334 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/48 ,  H01L25/03 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking.

摘要翻译： 公开了一种散热半导体封装结构及其制造方法。 该方法包括：在至少半导体芯片和封装单元上布置并电连接到芯片载体; 在所述封装单元的顶表面上设置有经由所述平坦部分具有平坦部分和支撑部分的散热元件; 在由散热元件的平坦部分和支撑部分形成的接收空间中接收封装单元和半导体芯片; 以及在芯片载体密封剂上形成以封装封装单元，半导体芯片和散热元件。 散热元件消散封装单元产生的热量，提供EMI屏蔽，防止封装单元与密封剂之间的分层，降低热阻，防止开裂。

公开(公告)号：US20090096115A1

公开(公告)日：2009-04-16

申请号：US11818050

申请日：2007-06-12

申请人： Chien-Ping Huang ,  Han-Ping Pu ,  Ho-Yi Tsai

发明人： Chien-Ping Huang ,  Han-Ping Pu ,  Ho-Yi Tsai

IPC分类号： H01L23/42 ,  H01L21/02 ,  H01L23/28

CPC分类号： H01L23/4334 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method for fabricating the same are disclosed. The present invention discloses mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interfacial layer or a heat-dissipating member having the interfacial layer on the semiconductor chip, and forming an encapsulant for covering the semiconductor chip, the interfacial layer or the heat dissipating member. The method further includes cutting the encapsulant along edges of the interfacial layer, and removing the redundant encapsulant on the interfacial layer so as to expose the semiconductor chip or the heat-dissipating member without forming burr or heavily wearing cutting tools.

摘要翻译： 公开了一种半导体封装及其制造方法。 本发明公开了将半导体芯片安装并电连接到芯片载体上，在半导体芯片上形成具有界面层的界面层或散热构件，并形成用于覆盖半导体芯片，界面层或 散热构件 该方法还包括沿着界面层的边缘切割密封剂，以及去除界面层上的冗余密封剂，以便露出半导体芯片或散热构件，而不会形成毛刺或严重磨损的切削工具。

公开(公告)号：US20080213942A1

公开(公告)日：2008-09-04

申请号：US12074321

申请日：2008-03-03

申请人： Min-Shun Hung ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Wen-Tsung Tseng ,  Cheng-Hsu Hsiao

发明人： Min-Shun Hung ,  Ho-Yi Tsai ,  Chien-Ping Huang ,  Wen-Tsung Tseng ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/12 ,  H05K7/00

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

摘要： This invention provides a method for fabricating a semiconductor device and a carrier applied therein. The method includes the steps of: disposing a chip-mounted substrate in an opening of a carrier; forming at least a storage aperture and at least an inspection aperture in the carrier; infusing an adhesive into the storage aperture to fill a gap between the substrate and carrier with the adhesive by capillarity; determining whether the inspection aperture is filled with the adhesive to ascertain whether the gap is completely filled with the adhesive; in response to a positive result, performing a molding process to form a molding compound for encapsulating the chip; and performing implantation of solder ball and a singulation process to form a semiconductor device with desirable dimensions. The inspection aperture is inspected with a naked eye to determine whether the gap is completely filled with the adhesive, thereby reducing inspection costs and increasing yields of products with no additional packaging costs.

摘要翻译： 本发明提供一种用于制造应用于其中的半导体器件和载体的方法。 该方法包括以下步骤：将芯片安装的基板设置在载体的开口中; 在所述载体中至少形成存储孔径和至少一个检查孔; 将粘合剂注入到存储孔中，以通过毛细管力用粘合剂填充基底和载体之间的间隙; 确定检查孔是否填充有粘合剂以确定间隙是否完全被粘合剂填充; 响应于积极的结果，进行成型处理以形成用于封装芯片的模塑料; 并且执行焊球的注入和单一化处理以形成具有所需尺寸的半导体器件。 检查孔径用肉眼检查以确定间隙是否完全充满粘合剂，从而降低检查成本并提高产品的产量，而不需要额外的包装成本。

公开(公告)号：US20080017977A1

公开(公告)日：2008-01-24

申请号：US11801625

申请日：2007-05-10

申请人： Wen-Tsung Tseng ,  Chien-Ping Huang ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

发明人： Wen-Tsung Tseng ,  Chien-Ping Huang ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

IPC分类号： H01L23/34

CPC分类号： H01L23/4334 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A heat dissipating semiconductor package and a heat dissipating structure thereof are provided. The heat dissipating structure includes an outer surface, consecutive recessed step portions, and a pressure-releasing groove. The outer surface is exposed from an encapsulant made of a molding compound. The step portions are formed at an edge of the outer surface and have decreasing depths wherein the closer a step portion to a central position of the outer surface, the smaller the depth of this step portion is. The pressure-releasing groove is disposed next to and deeper than the innermost one of the step portions. A molding compound flows to the step portions and absorbs heat from an encapsulation mold quickly, such that a flowing speed of the molding compound is reduced. Pressure suffered by air remaining at the step portions is released through the pressure-releasing groove, thereby preventing flashes of the molding compound and resin bleeding.

摘要翻译： 提供散热半导体封装及其散热结构。 散热结构包括外表面，连续凹进的台阶部分和压力释放槽。 外表面从由模塑料制成的密封剂暴露。 台阶部分形成在外表面的边缘处并且具有减小的深度，其中台阶部分越接近外表面的中心位置，该阶梯部分的深度越小。 压力释放槽设置在步骤部分的最内侧之上并深度。 模塑料流到台阶部分并迅速从封装模具吸收热量，从而降低模塑料的流动速度。 通过压力释放槽释放在台阶部分残留的空气所产生的压力，从而防止模塑料的闪烁和树脂渗色。

公开(公告)号：US06603196B2

公开(公告)日：2003-08-05

申请号：US09820135

申请日：2001-03-28

申请人： Ming-Hsun Lee ,  Ho-Yi Tsai

发明人： Ming-Hsun Lee ,  Ho-Yi Tsai

IPC分类号： H01L23495

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A leadframe-based semiconductor package is proposed for the packaging of a semiconductor device, such as a multi-media card (MMC) chipset. The proposed semiconductor package is characterized by the use of a leadframe, rather than BT substrate or film, as the chip carrier for MMC chipset. The leadframe includes a supporting bar, a chip-supporting structure arranged at a downset position in relation to the supporting bar; and a plurality of leads, each lead including an outer-lead portion and an inner-lead portion; wherein the outer-lead portion is levelly linked to the supporting bar, while the inner-lead portion is arranged beside the chip-supporting structure and linked to the outer-lead portion via an intermediate-lead portion. The leadframe can be either the type having die pad or the type having no die pad. In the case of the type having die pad, a semiconductor chip is mounted on the die pad; and in the case of the type having no die pad, one or more semiconductor chips are mounted over an elongated part of the inner-lead portions of the leads. The use of leadframe allows the MMC package to be manufactured without having to include a lidding process, so that the MMC manufacture can be carried out in a less complex and more cost-effective manner.

公开(公告)号：US08420521B2

公开(公告)日：2013-04-16

申请号：US12955256

申请日：2010-11-29

申请人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

发明人： Fang-Lin Tsai ,  Ho-Yi Tsai ,  Han-Ping Pu ,  Cheng-Hsu Hsiao

IPC分类号： H01L21/44

CPC分类号： H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/50 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01077 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

摘要翻译： 提供半导体封装的堆叠结构以及制造叠层结构的方法。 在上半导体封装的衬底的表面上和与下半导体封装的密封剂周围的位置对应的位置处形成多个电连接焊盘和虚拟焊盘。 将焊球植入电连接焊盘和虚拟焊盘。 上半导体封装安装在下半导体封装上。 上半导体封装通过注入电连接焊盘的焊球电连接到下半导体封装，并且下半导体封装的密封剂被植入到虚拟焊盘中的焊球围绕并限制。 因此，上半导体封装被适当且牢固地定位在下半导体封装上，而不会发生上下半导体封装之间的未对准。