公开(公告)号：US20130099371A1

公开(公告)日：2013-04-25

申请号：US13278621

申请日：2011-10-21

Applicant: Ming-Da CHENG ,  Kuei-Wei HUANG ,  Yu-Peng TSAI ,  Cheng-Ting CHEN ,  Hsiu-Jen LIN ,  Chung-Shi LIU

Inventor： Ming-Da CHENG ,  Kuei-Wei HUANG ,  Yu-Peng TSAI ,  Cheng-Ting CHEN ,  Hsiu-Jen LIN ,  Chung-Shi LIU

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/01029 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01022 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The silver (Ag) content in the solder layer is between 0.5 and 1.8 weight percent.

Abstract translation: 半导体封装包括具有导电迹线的工件和具有导电柱的芯片。 芯片附着在工件上，并且在导电柱和导电迹线之间形成焊点区域。 焊料层中的银（Ag）含量为0.5-1.8重量％。

公开(公告)号：US20130143364A1

公开(公告)日：2013-06-06

申请号：US13312395

申请日：2011-12-06

Applicant: Hsiu-Jen LIN ,  Chung-Shi LIU ,  Ming-Da CHENG ,  Chun-Cheng LIN ,  Yu-Peng TSAI ,  Cheng-Ting CHEN

Inventor： Hsiu-Jen LIN ,  Chung-Shi LIU ,  Ming-Da CHENG ,  Chun-Cheng LIN ,  Yu-Peng TSAI ,  Cheng-Ting CHEN

IPC: H01L21/58

Abstract: A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Abstract translation: 一种方法包括在具有至少一个焊料凸块的衬底上进行真空退火以减少在至少一个焊料凸块的界面处的空隙。 模具安装在基板上。

公开(公告)号：US20220071333A1

公开(公告)日：2022-03-10

申请号：US17039882

申请日：2020-09-30

Applicant: Cheng-Ting CHEN

Inventor： Cheng-Ting CHEN

IPC: A42B3/12 ,  A42B3/14

Abstract: The present invention provides a safety helmet inner lining adjustable for suitable wearing, consisting of: a covering body, which has an inner side surface that contacts a user's head and an outer side surface relative to the inner side surface; at least one interlayer pocket, which is disposed on the outer side surface of the covering body; and at least one cushiony pad, which is suitable for placement inside the interlayer pocket. A user is able to place the cushiony pads of suitable thickness into the interlayer pockets at preset positions according to the user's to head shape and dimensions. The inner lining is then put onto the head and a safety helmet put on top. The cushiony pads enable correcting the interspace between the user's head and the safety helmet, thereby allowing suitable and perfect fitting of the safety helmet that ensures safety of the wearer.

公开(公告)号：US20120065764A1

公开(公告)日：2012-03-15

申请号：US12879278

申请日：2010-09-10

Applicant: Chen-FA LU ,  Cheng-Ting CHEN ,  James HU ,  Chung-Shi LIU

Inventor： Chen-FA LU ,  Cheng-Ting CHEN ,  James HU ,  Chung-Shi LIU

IPC: G06F17/00

CPC classification number: G05B19/41875 ,  B24B37/005

Abstract: Processing defects arising during processing of a semiconductor wafer prior to back-grinding are reduced with systems and methods of sensor placement. One or more holes are bored into a chuck table for receiving semiconductor wafers, or a support table next to the chuck table. One or more sensors are disposed in the holes for monitoring parameters during a pre-back-grinding (PBG) process. A control box converts a set of signals received from the sensors. A computer-implemented process control tool receives the converted set of signals from the control box and determines whether the PBG process will continue.

Abstract translation: 通过传感器放置的系统和方法，减少了在后研磨之前处理半导体晶片期间产生的加工缺陷。 将一个或多个孔钻入用于接收半导体晶片的卡盘台，或者在卡盘台旁边的支撑台。 一个或多个传感器设置在孔中，用于在前置后研磨（PBG）过程期间监测参数。 控制箱转换从传感器接收的一组信号。 计算机实现的过程控制工具从控制箱接收转换的信号集，并确定PBG过程是否继续。

公开(公告)号：US20130285238A1

公开(公告)日：2013-10-31

申请号：US13460412

申请日：2012-04-30

Applicant: Meng-Tse CHEN ,  Hsiu-Jen LIN ,  Chih-Wei LIN ,  Cheng-Ting CHEN ,  Ming-Da CHENG ,  Chung-Shi LIU

Inventor： Meng-Tse CHEN ,  Hsiu-Jen LIN ,  Chih-Wei LIN ,  Cheng-Ting CHEN ,  Ming-Da CHENG ,  Chung-Shi LIU

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/1134 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.

Abstract translation: 半导体封装结构包括衬底，与衬底结合的管芯，以及将管芯连接到衬底的一个或多个柱塞凸块结构，其中每个凸起凸块结构具有柱形凸起和封装凸起凸起的焊球，以增强 散热并减少半导体封装结构中的高应力集中。