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公开(公告)号：US07068122B2
公开(公告)日：2006-06-27
申请号：US10954107
申请日：2004-09-28
CPC分类号： H01P5/10
摘要： A miniaturized multi-layer balun includes a pair of capacitive elements, at least one section of broadside coupled lines connected in series to an unbalanced and two balanced ports through a pair of transmission lines. Each section has first and second coupled lines. A ground connection is located between two central second coupled lines, and connected to a ground. By means of a multi-layer structure and the addition of a ground connection, the balun of the invention can be fabricated with five conductor layers. This not only greatly decreases the size of the balun device, but also enhances the stability of the device. From the measured return loss and differences in magnitude and phase to the frequency response, it shows that the balun of the invention has good impedance match.
摘要翻译： 小型化多层平衡 - 不平衡变换器包括一对电容元件，通过一对传输线与至不平衡端口和两个平衡端口串联连接的至少一个宽边耦合线段。 每个部分具有第一和第二耦合线。 接地连接位于两个中央第二耦合线之间，并连接到地面。 通过多层结构和添加接地连接，本发明的平衡 - 不平衡变换器可以用五个导体层制造。 这不仅大大减小了平衡 - 转换装置的尺寸，而且还增强了装置的稳定性。 从测量的回波损耗和幅度和相位的差异到频率响应，表明本发明的平衡 - 不平衡变换器具有良好的阻抗匹配。
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公开(公告)号：US20060066415A1
公开(公告)日：2006-03-30
申请号：US10954107
申请日：2004-09-28
IPC分类号： H01P5/10
CPC分类号： H01P5/10
摘要： A miniaturized multi-layer balun includes a pair of capacitive elements, at least one section of broadside coupled lines connected in series to a unbalanced and two balanced ports through a pair of transmission lines. Each section has first and second coupled lines. A ground connection is located between two central second coupled lines, and connected to a ground. By means of a multi-layer structure and the addition of a ground connection, the balun of the invention can be fabricated with five conductor layers. This not only greatly decreases the size of the balun device, but also enhances the stability of the device. From the measured return loss and differences in magnitude and phase to the frequency response, it shows that the balun of the invention has good impedance match.
摘要翻译： 小型化多层平衡 - 不平衡变换器包括一对电容元件，通过一对传输线与至少一个不平衡端口和两个平衡端口串联连接的至少一个宽边耦合线段。 每个部分具有第一和第二耦合线。 接地连接位于两个中央第二耦合线之间，并连接到地面。 通过多层结构和添加接地连接，本发明的平衡 - 不平衡变换器可以用五个导体层制造。 这不仅大大减小了平衡 - 转换装置的尺寸，而且还增强了装置的稳定性。 从测量的回波损耗和幅度和相位的差异到频率响应，表明本发明的平衡 - 不平衡变换器具有良好的阻抗匹配。
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公开(公告)号：US07529103B2
公开(公告)日：2009-05-05
申请号：US11438363
申请日：2006-05-23
申请人： Chang-Sheng Chen , Uei-Ming Jow , Ying-Jiunn Lai , Chin-Sun Shyu
发明人： Chang-Sheng Chen , Uei-Ming Jow , Ying-Jiunn Lai , Chin-Sun Shyu
IPC分类号： H05K1/14
CPC分类号： H05K1/162 , H03H7/09 , H03H7/1775 , H03H2001/0085 , H05K3/4626 , H05K3/4688 , H05K2201/09236 , H05K2201/09672
摘要： A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.
摘要翻译： 嵌入滤光器的多层印刷电路板，使用由至少由至少低介电材料层叠的高介电材料形成的复合多层印刷电路板的多层印刷电路板。 多个串联或并联电容器设置在复合多层印刷电路板中以形成滤波器。 至少一个电容器是设置在低电介质材料上的叉指电容器。 叉指电容器的金属电极位于同一平面上，使得金属电极的面积或金属电极之间的间隔可以预先调整以精确地控制诸如滤波器的中心频率和传输损耗之类的电气特性 。 也可以防止在制造复合多层印刷电路板时引起的对准误差所引起的问题。
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4.发明授权Film resistor embedded in multi-layer circuit board and manufacturing method thereof 有权嵌入多层电路板的薄膜电阻及其制造方法公开(公告)号：US07830241B2
公开(公告)日：2010-11-09
申请号：US11485785
申请日：2006-07-12
申请人： Ying-Jiunn Lai , Chin-Sun Shyu , Chang-Sheng Chen , Uei-Ming Jow
发明人： Ying-Jiunn Lai , Chin-Sun Shyu , Chang-Sheng Chen , Uei-Ming Jow
IPC分类号： H01C1/012
CPC分类号： H05K1/167 , H01C1/14 , H01C7/003 , H05K3/4644 , H05K2201/09509 , H05K2201/09563 , H05K2203/1453
摘要： A resistor structure embedded in a multi-layer circuit board and manufacturing method thereof are provided. Resistive material is coated on any layer among the multi-layer circuit board, and two symmetric electrodes are formed in the geometric center of the resistive material area. The two electrodes are disposed in the resistive material layer and are covered by the resistive material. And the two electrodes are led out from respective bores at the central position of the resistive electrodes, for connecting to any other metal layer. This resistor structure can avoid the unstable resistance when the coated resistor is operated at high frequency, and also avoid the formation untrimmed edges during coating that affects the precision of resistance.
摘要翻译： 提供一种嵌入多层电路板的电阻结构及其制造方法。 电阻材料涂覆在多层电路板中的任何层上，并且在电阻材料区域的几何中心形成两个对称电极。 两个电极设置在电阻材料层中并被电阻材料覆盖。 并且两个电极从电阻电极的中心位置处的各个孔引出，用于连接到任何其它金属层。 这种电阻结构可以避免涂层电阻器在高频率下运行时的不稳定电阻，并且避免了在涂层期间形成未经修整的边缘，影响电阻精度。
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公开(公告)号：US20090051469A1
公开(公告)日：2009-02-26
申请号：US12260254
申请日：2008-10-29
申请人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
IPC分类号： H01P1/00
CPC分类号： H01L23/14 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01G4/30 , H01G4/40 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/162 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0187 , H05K2201/086 , H05K2201/09672 , H01L2924/00
摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 可以在每个衬底上方形成一个或多个磁导块，从而可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。
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公开(公告)号：US20080093113A1
公开(公告)日：2008-04-24
申请号：US11861297
申请日：2007-09-26
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lay , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
IPC分类号： H05K1/16
CPC分类号： H05K1/167 , H05K1/0224 , H05K1/025 , H05K1/0298 , H05K2201/0792 , H05K2201/09681 , H05K2201/0969
摘要： A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.
摘要翻译： 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。
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公开(公告)号：US08174840B2
公开(公告)日：2012-05-08
申请号：US12260254
申请日：2008-10-29
申请人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Chang-Sheng Chen , Chin-Sun Shyu , Min-Lin Lee , Shinn-Juh Lay , Ying-Jiunn Lai
IPC分类号： H05K1/16
CPC分类号： H01L23/14 , H01F17/0006 , H01F41/046 , H01F2017/0066 , H01G4/30 , H01G4/40 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/162 , H05K1/165 , H05K3/4626 , H05K3/4652 , H05K3/4655 , H05K3/4688 , H05K2201/0187 , H05K2201/086 , H05K2201/09672 , H01L2924/00
摘要： A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.
摘要翻译： 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 一个或多个导磁块可以形成在每个衬底之上，使得可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。
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8.发明申请Circuit board with embedded components and manufacturing and measuring method thereof 有权具有嵌入式元件的电路板及其制造及测量方法公开(公告)号：US20080035371A1
公开(公告)日：2008-02-14
申请号：US11882814
申请日：2007-08-06
申请人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lai , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
发明人： Uei-Ming Jow , Min-Lin Lee , Shinn-Juh Lai , Chin-Sun Shyu , Chang-Sheng Chen , Ying-Jiunn Lai
CPC分类号： G01R31/2818 , G01R31/2813 , G01R31/2839 , H05K1/0268 , H05K1/0298 , H05K1/16 , H05K3/46 , H05K2203/162 , Y10T29/49004
摘要： A circuit board with embedded components includes a plurality of embedded components and at least one transmission line electrically connected to at least one of the embedded components and having a terminal circuit. Therefore, a measuring device is used to be electrically connected to the transmission line and send out a signal, so as to receive a corresponding reflected signal, and then, compare the received reflected signal with a signal pattern in the database to obtain an electrical parameter of the embedded component.
摘要翻译： 具有嵌入式组件的电路板包括多个嵌入式组件和至少一个电连接到至少一个嵌入式组件并具有终端电路的传输线。 因此，使用测量装置电连接到传输线并发出信号以接收对应的反射信号，然后将接收的反射信号与数据库中的信号模式进行比较，以获得电参数 的嵌入式组件。
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9.发明申请Film resistor embedded in multi-layer circuit board and manufacturing method thereof 有权嵌入多层电路板的薄膜电阻及其制造方法公开(公告)号：US20070222551A1
公开(公告)日：2007-09-27
申请号：US11485785
申请日：2006-07-12
申请人： Ying-Jiunn Lai , Chin-Sun Shyu , Chang-Sheng Chen , Uei-Ming Jow
发明人： Ying-Jiunn Lai , Chin-Sun Shyu , Chang-Sheng Chen , Uei-Ming Jow
IPC分类号： H01C1/012
CPC分类号： H05K1/167 , H01C1/14 , H01C7/003 , H05K3/4644 , H05K2201/09509 , H05K2201/09563 , H05K2203/1453
摘要： A resistor structure embedded in a multi-layer circuit board and manufacturing method thereof are provided. Resistive material is coated on any layer among the multi-layer circuit board, and two symmetric electrodes are formed in the geometric center of the resistive material area. The two electrodes are disposed in the resistive material layer and are covered by the resistive material. And the two electrodes are led out from respective bores at the central position of the resistive electrodes, for connecting to any other metal layer. This resistor structure can avoid the unstable resistance when the coated resistor is operated at high frequency, and also avoid the formation untrimmed edges during coating that affects the precision of resistance.
摘要翻译： 提供一种嵌入多层电路板的电阻结构及其制造方法。 电阻材料涂覆在多层电路板中的任何层上，并且在电阻材料区域的几何中心形成两个对称电极。 两个电极设置在电阻材料层中并被电阻材料覆盖。 并且两个电极从电阻电极的中心位置处的各个孔引出，用于连接到任何其它金属层。 这种电阻结构可以避免涂层电阻器在高频率下运行时的不稳定电阻，并且避免了在涂层期间形成未经修整的边缘，影响电阻精度。
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公开(公告)号：US20070222031A1
公开(公告)日：2007-09-27
申请号：US11456094
申请日：2006-07-07
申请人： Uei-Ming Jow , Chang-Sheng Chen , Ying-Jiunn Lai , Chin-Sun Shyu
发明人： Uei-Ming Jow , Chang-Sheng Chen , Ying-Jiunn Lai , Chin-Sun Shyu
IPC分类号： H01L29/00
CPC分类号： H05K1/162 , H01G4/232 , H01G4/306 , H01L23/50 , H01L23/5223 , H01L28/10 , H01L28/60 , H01L2924/0002 , H01L2924/3011 , H05K1/0298 , H05K2201/09236 , H05K2201/09672 , H01L2924/00
摘要： A capacitor structure with a cross-coupling design is provided. In the capacitor structure, conductive lines or electrode plates are coupled together by cross coupling an electrode above or below or aside the other electrode. By cross coupling and fewer vias, the largest capacitance value can be obtained within a minimum area. The capacitor structure provided can also be applied to a high-frequency high-speed module or system to enhance noise inhibition capability of a capacitive substrate.
摘要翻译： 提供了具有交叉耦合设计的电容器结构。 在电容器结构中，通过在另一电极上方或下方或旁边交叉耦合电极将导线或电极板耦合在一起。 通过交叉耦合和较少的通孔，可以在最小区域内获得最大的电容值。 所提供的电容器结构也可以应用于高频高速模块或系统，以增强电容性基板的噪声抑制能力。
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