公开(公告)号：US20110248394A1

公开(公告)日：2011-10-13

申请号：US13085446

申请日：2011-04-12

申请人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

发明人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

摘要翻译： 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

公开(公告)号：US08525310B2

公开(公告)日：2013-09-03

申请号：US13085446

申请日：2011-04-12

申请人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

发明人： Nan-Jang Chen ,  Chun-Wei Chang ,  Sheng-Ming Chang ,  Che-Yuan Jao ,  Ching-Chih Li ,  Nan-Cheng Chen

IPC分类号： H01L23/495

CPC分类号： H01L24/49 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads disposed along peripheral edges of the die pad; a ground bar between the leads and the die pad; and a plurality of bridges connecting the ground bar with the die pad, wherein a gap between two adjacent bridges has a length that is equal to or less than 3 mm.

摘要翻译： 半导体封装包括管芯焊盘; 安装在管芯焊盘上的半导体管芯; 沿着所述管芯焊盘的周缘设置的多个引线; 引线和芯片焊盘之间的接地棒; 以及将接地棒与管芯焊盘连接的多个桥，其中两个相邻桥之间的间隙具有等于或小于3mm的长度。

公开(公告)号：US20100207260A1

公开(公告)日：2010-08-19

申请号：US12766080

申请日：2010-04-23

申请人： Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

发明人： Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed.

摘要翻译： 提供电子包装。 电子封装包括其上附着有管芯的管芯焊盘。 多个引线围绕芯片焊盘并与其间隔开以在其间限定环形间隙。 至少一个第一公共电极棒处于环形间隙中并且基本上与芯片焊盘共面，其中多个引线中的至少一个延伸到第一公共电极棒。 模塑料部分地封装芯片焊盘和第一公共电极棒，使得裸片焊盘和第一公共电极棒的底表面露出。 第一公共电极棒的长度基本上等于面对第一公共电极棒的模具一侧的多个电源或接地焊盘中的两个焊盘之间的预定距离。 还公开了一种具有电子封装的电子设备。

公开(公告)号：US08283757B2

公开(公告)日：2012-10-09

申请号：US12766080

申请日：2010-04-23

申请人： Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

发明人： Nan-Cheng Chen ,  Nan-Jang Chen ,  Ching-Chih Li

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed.

摘要翻译： 提供电子包装。 电子封装包括其上附着有管芯的管芯焊盘。 多个引线围绕芯片焊盘并与其间隔开以在其间限定环形间隙。 至少一个第一公共电极棒处于环形间隙中并且基本上与芯片焊盘共面，其中多个引线中的至少一个延伸到第一公共电极棒。 模塑料部分地封装芯片焊盘和第一公共电极棒，使得裸片焊盘和第一公共电极棒的底表面露出。 第一公共电极棒的长度基本上等于面对第一公共电极棒的模具一侧的多个电源或接地焊盘中的两个焊盘之间的预定距离。 还公开了一种具有电子封装的电子设备。

公开(公告)号：US07561481B2

公开(公告)日：2009-07-14

申请号：US11760955

申请日：2007-06-11

申请人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

发明人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

IPC分类号： G11C7/00

CPC分类号： G06F13/1694

摘要： Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

摘要翻译： 提供了存储器控制器及其优化焊盘序列的方法。 首先提供用于至少一个存储器件的印刷电路板上的至少两个不同的优选迹线序列。 然后提供一个存储器控制器以具有核心逻辑电路，多个输入/输出（I / O）设备和重新启动器。 核心逻辑有I / O端子。 单个芯片上的每个I / O设备都有一个焊盘。 重排器耦合在核心逻辑电路和输入/输出设备之间，可编程以将输入/输出设备选择性地连接到输入/输出端子。 后续程序随后被编程为选择并将输入/输出设备的一部分连接到输入/输出端子，使得基本上支持不同优选轨迹序列之一。

公开(公告)号：US20080304352A1

公开(公告)日：2008-12-11

申请号：US11760955

申请日：2007-06-11

申请人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

发明人： Nan-Cheng Chen ,  Chih-Hui Kuo ,  Jui-Hsing Tseng ,  Ching-Chih Li ,  Pei-San Chen

IPC分类号： G11C8/06

CPC分类号： G06F13/1694

摘要： Memory controllers and methods of optimizing pad sequences thereof are provided. At least two different preferred trace sequences on printed circuit boards for at least one memory device are first provided. One memory controller is then provided to have a core logic circuit, a plurality of input/output (I/O) devices, and a reorderer. The core logic has I/O terminals. Each I/O device on the single chip has a pad. The reorderer is coupled between the core logic circuit and the input/output devices, programmable to selectively connect the input/output devices to the input/output terminals. The reorderer is later programmed to select and connect a portion of the input/output devices to the input/output terminals such that one of the different preferred trace sequences is substantially supported.

摘要翻译： 提供了存储器控制器及其优化焊盘序列的方法。 首先提供用于至少一个存储器件的印刷电路板上的至少两个不同的优选迹线序列。 然后提供一个存储器控制器以具有核心逻辑电路，多个输入/输出（I / O）设备和重新启动器。 核心逻辑有I / O端子。 单个芯片上的每个I / O设备都有一个焊盘。 重排器耦合在核心逻辑电路和输入/输出设备之间，可编程以将输入/输出设备选择性地连接到输入/输出端子。 后续程序随后被编程为选择并将输入/输出设备的一部分连接到输入/输出端子，使得基本上支持不同优选轨迹序列之一。

公开(公告)号：US20080080142A1

公开(公告)日：2008-04-03

申请号：US11763630

申请日：2007-06-15

申请人： Nan-Cheng Chen ,  Chun-Wei Chang ,  Chao-Wei Tseng

发明人： Nan-Cheng Chen ,  Chun-Wei Chang ,  Chao-Wei Tseng

IPC分类号： H05K7/20

CPC分类号： H05K7/205 ,  H05K1/0203 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/341 ,  H05K3/3452 ,  H05K2201/0715 ,  H05K2201/09054 ,  H05K2201/10303 ,  H05K2201/10477 ,  H05K2201/10727

摘要： An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.

摘要翻译： 具有增强散热性的电子设备。 印刷电路板设置在壳体中，并且包括第一金属接地层，第二金属接地层和金属连接部分。 第一金属接地层与第二金属接地层相对。 金属连接部分连接在第一和第二金属接地层之间。 第二金属接地层连接到外壳。 芯片电连接到印刷电路板，并且包括模具和连接到模具并与第一金属接地层焊接的导热部分。 由芯片产生的热量通过导热部分，第一金属接地层，金属连接部分和第二金属接地层传导到壳体。

公开(公告)号：US20090236707A1

公开(公告)日：2009-09-24

申请号：US12473477

申请日：2009-05-28

申请人： Nan-Cheng Chen ,  Chun-Wei Chang ,  Chao-Wei Tseng

发明人： Nan-Cheng Chen ,  Chun-Wei Chang ,  Chao-Wei Tseng

IPC分类号： H01L23/34 ,  H01L23/495 ,  H01L23/498 ,  H01L23/48

CPC分类号： H05K7/205 ,  H05K1/0203 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/341 ,  H05K3/3452 ,  H05K2201/0715 ,  H05K2201/09054 ,  H05K2201/10303 ,  H05K2201/10477 ,  H05K2201/10727

摘要： An electronic device with enhanced heat spread. A printed circuit board is disposed in a casing and includes a first metal ground layer, a second metal ground layer, and a metal connecting portion. The first metal ground layer is opposite the second metal ground layer. The metal connecting portion is connected between the first and second metal ground layers. The second metal ground layer is connected to the casing. A chip is electrically connected to the printed circuit board and includes a die and a heat-conducting portion connected to the die and soldered with the first metal ground layer. Heat generated by the chip is conducted to the casing through the heat-conducting portion, first metal ground layer, metal connecting portion, and second metal ground layer.

摘要翻译： 具有增强散热性的电子设备。 印刷电路板设置在壳体中，并且包括第一金属接地层，第二金属接地层和金属连接部分。 第一金属接地层与第二金属接地层相对。 金属连接部分连接在第一和第二金属接地层之间。 第二金属接地层连接到外壳。 芯片电连接到印刷电路板，并且包括模具和连接到模具并与第一金属接地层焊接的导热部分。 由芯片产生的热量通过导热部分，第一金属接地层，金属连接部分和第二金属接地层传导到壳体。

公开(公告)号：US20130133193A1

公开(公告)日：2013-05-30

申请号：US13305502

申请日：2011-11-28

申请人： Chih-Tai Hsu ,  Nan-Cheng Chen ,  Chih-Ming Chiang ,  Hung-Chang Hung ,  Xin Zhong

发明人： Chih-Tai Hsu ,  Nan-Cheng Chen ,  Chih-Ming Chiang ,  Hung-Chang Hung ,  Xin Zhong

IPC分类号： H05K3/34 ,  H05K3/12

CPC分类号： H01L23/49503 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/00015 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/1225 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/09427 ,  H05K2201/10803 ,  H05K2201/10969 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/53174 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad.

摘要翻译： 本发明提供了一种用于高级四边形扁平无铅封装工艺的表面贴装技术工艺和与其一起使用的模板。 用于高级四边形扁平无铅封装的表面贴装技术工艺包括提供印刷电路板。 具有第一开口的模板安装在印刷电路板上。 印刷焊膏通过第一开口形成第一焊膏图案。 模具被取下。 执行部件放置处理以将包括管芯焊盘的高级四边形扁平无引线封装放置在印刷电路板上，其中第一焊膏图案接触管芯焊盘的下表面，并且将第一开口与 芯片焊盘的下表面在1:2与1:10之间。 进行回流处理以熔化第一焊膏图案以围绕管芯焊盘的侧壁。

公开(公告)号：US20120032314A1

公开(公告)日：2012-02-09

申请号：US13280368

申请日：2011-10-25

申请人： Nan-Cheng Chen ,  Chih-Tai Hsu

发明人： Nan-Cheng Chen ,  Chih-Tai Hsu

IPC分类号： H01L23/498 ,  H01L23/495

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5382 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A package-on-package includes a package carrier; a semiconductor die assembled face-down to a chip side of the package carrier; a rewiring laminate structure between the semiconductor die and the package carrier; a plurality of bumps arranged on the rewiring laminate structure for electrically connecting the semiconductor die with the package carrier; and an IC package mounted on the package carrier. The IC package and the semiconductor die are at least partially overlapped.

摘要翻译： 封装包装包括一个封装载体; 从封装载体的芯片侧面朝下组装的半导体芯片; 半导体管芯和封装载体之间的重新配线层叠结构; 布置在重新布线层压结构上的多个凸起，用于将半导体管芯与封装载体电连接; 以及安装在封装载体上的IC封装。 IC封装和半导体管芯至少部分重叠。