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    SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS
    4.
    发明申请
    SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS 有权
    多元化过程中的单次接触

    公开(公告)号：US20120326313A1

    公开(公告)日：2012-12-27

    申请号：US13170095

    申请日：2011-06-27

    申请人： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

    发明人： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

    摘要翻译： 仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。 该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。 该方法可以包括在不同的去除条件下从多层结构去除材料。 还公开了具有不同尺寸的多个空腔的多层镶嵌结构。 空腔可以具有平滑的内壁表面。 结构的层可以直接接触。 空腔可以用导电金属或绝缘体填充。 进一步公开了使用这些方法和结构的多层半导体器件。

    LOW STRESS VIAS
    6.
    发明申请
    LOW STRESS VIAS 有权
    低应力VIAS

    公开(公告)号：US20130026645A1

    公开(公告)日：2013-01-31

    申请号：US13193814

    申请日：2011-07-29

    申请人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    发明人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    IPC分类号： H01L23/48 ,  H01L21/283

    CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

    摘要： A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

    摘要翻译： 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

    Low stress vias
    7.
    发明授权
    Low stress vias 有权
    低压通孔

    公开(公告)号：US08816505B2

    公开(公告)日：2014-08-26

    申请号：US13193814

    申请日：2011-07-29

    申请人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    发明人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    IPC分类号： H01L23/48 ,  H01L21/283

    CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

    摘要： A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

    摘要翻译： 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

    Vias in porous substrates
    9.
    发明授权
    Vias in porous substrates 有权
    多孔基材中的通孔

    公开(公告)号：US08975751B2

    公开(公告)日：2015-03-10

    申请号：US13092495

    申请日：2011-04-22

    申请人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia

    发明人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia

    IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15 ,  H01L23/48 ,  H01L23/498

    CPC分类号： H01L21/76877 ,  H01L21/486 ,  H01L21/76837 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.

    摘要翻译： 微电子单元可以包括其中具有前表面和后表面的基板和其中的有源半导体器件，所述基板具有布置成在后表面的区域上的对称或不对称分布的多个开口，连接到第一和第二导电通孔的第一和第二导电通孔 在前表面暴露的焊盘，在相应的一个开口内延伸的多个第一和第二导电互连，以及暴露以与外部元件互连的第一和第二导电触点。 多个第一导电互连可以通过所述多个开口中的至少一个与所述多个第二导电互连部分开，所述至少一个开口至少部分地填充有绝缘材料。 开口的分布可以包括在第一方向上间隔开的至少m个开口和在横向于第一方向的第二方向上间隔开的n个开口。

    VIAS IN POROUS SUBSTRATES
    10.
    发明申请
    VIAS IN POROUS SUBSTRATES 有权
    多孔基材中的VIAS

    公开(公告)号：US20120267789A1

    公开(公告)日：2012-10-25

    申请号：US13092495

    申请日：2011-04-22

    申请人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia

    发明人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh ,  Piyush Savalia

    IPC分类号： H01L23/48 ,  H01L21/28

    CPC分类号： H01L21/76877 ,  H01L21/486 ,  H01L21/76837 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.

    摘要翻译： 微电子单元可以包括其中具有前表面和后表面的基板和其中的有源半导体器件，所述基板具有布置成在后表面的区域上的对称或不对称分布的多个开口，连接到第一和第二导电通孔的第一和第二导电通孔 在前表面暴露的焊盘，在相应的一个开口内延伸的多个第一和第二导电互连，以及暴露以与外部元件互连的第一和第二导电触点。 多个第一导电互连可以通过所述多个开口中的至少一个与所述多个第二导电互连部分开，所述至少一个开口至少部分地填充有绝缘材料。 开口的分布可以包括在第一方向上间隔开的至少m个开口和在横向于第一方向的第二方向上间隔开的n个开口。