公开(公告)号：US08637964B2

公开(公告)日：2014-01-28

申请号：US13281548

申请日：2011-10-26

Applicant: Patrick Jones ,  Andre Christmann ,  Daniel Domes

Inventor： Patrick Jones ,  Andre Christmann ,  Daniel Domes

IPC: H01R9/00 ,  H01L31/119

CPC classification number: H01L25/07 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A power module includes a substrate including an insulating member and a patterned metallization on the insulating member. The patterned metallization is segmented into a plurality of spaced apart metallization regions. Adjacent ones of the metallization regions are separated by a groove which extends through the patterned metallization to the insulating member. A first power transistor circuit includes a first power switch attached to a first one of the metallization regions and a second power switch attached to a second one of the metallization regions adjacent a first side of the first metallization region. A second power transistor circuit includes a third power switch attached to the first metallization region and a fourth power switch attached to a third one of the metallization regions adjacent a second side of the first metallization region which opposes the first side. The second power transistor circuit mirrors the first power transistor circuit.

Abstract translation: 功率模块包括在绝缘构件上包括绝缘构件和图案化金属化的衬底。 图案化金属化被分割成多个间隔开的金属化区域。 相邻的金属化区域被延伸通过图案化金属化的凹槽分隔成绝缘构件。 第一功率晶体管电路包括附接到第一金属化区域的第一功率开关和附接到第一金属化区域的第一侧附近的第二金属化区域的第二功率开关。 第二功率晶体管电路包括附接到第一金属化区域的第三电力开关和附接到与第一侧相对的第一金属化区域的第二侧附近的第三金属化区域的第四电力开关。 第二功率晶体管电路反射第一功率晶体管电路。

公开(公告)号：US20130094122A1

公开(公告)日：2013-04-18

申请号：US13271491

申请日：2011-10-12

Applicant: Daniel Domes ,  Reinhold Bayerer

Inventor： Daniel Domes ,  Reinhold Bayerer

IPC: H01G4/38 ,  H05K7/20 ,  H01G4/12

CPC classification number: H05K7/1432 ,  H01G2/06 ,  H01G4/40 ,  H01L2224/48472

Abstract: According to one embodiment of a capacitor module, the capacitor module includes a substrate having a metallization on a first side of the substrate, a plurality of connectors electrically coupled to the metallization and a plurality of capacitors disposed on the metallization. The plurality of capacitors includes a first set of capacitors electrically connected in parallel between a first set of the connectors and a second set of the connectors. The capacitor module further includes a housing enclosing the plurality of capacitors within the capacitor module.

Abstract translation: 根据电容器模块的一个实施例，电容器模块包括在衬底的第一侧上具有金属化的衬底，电耦合到金属化的多个连接器和设置在金属化上的多个电容器。 多个电容器包括并联电连接在第一组连接器和第二组连接器之间的第一组电容器。 电容器模块还包括封装电容器模块内的多个电容器的壳体。

公开(公告)号：US08729914B2

公开(公告)日：2014-05-20

申请号：US12943079

申请日：2010-11-10

Applicant: Daniel Domes

Inventor： Daniel Domes

IPC: G01R19/14

CPC classification number: H03K17/18

Abstract: A circuit arrangement includes: a reverse conducting IGBT configured to allow for conducting a load current in a forward direction and in a reverse direction, the IGBT having a load current path and a gate electrode; a gate control unit connected to the gate electrode and configured to activate or deactivate the IGBT by charging or, respectively, discharging the gate electrode in accordance with a gate control signal; a gate driver unit configured to detect whether the IGBT conducts current in the forward direction or the reverse direction by sensing a gate current caused by a change of a voltage drop across the load path due to a changing of the reverse conducting IGBT into its reverse conducting state, the gate control unit further configured to deactivate the IGBT or to prevent an activation of the IGBT via its gate electrode when the gate driver unit detects that the IGBT is in its reverse conducting state.

Abstract translation: 电路装置包括：反向导通IGBT，被配置为允许在正向和反向导通负载电流，所述IGBT具有负载电流路径和栅电极; 栅极控制单元，连接到所述栅电极并且被配置为通过根据栅极控制信号充电或分别放电所述栅电极来激活或去激活所述IGBT; 栅极驱动器单元，被配置为通过检测由于反向导通IGBT变为其反向导通而在负载路径上的电压降的变化引起的栅极电流来检测IGBT是正向还是反向导通电流 状态，门控制单元还被配置为当栅极驱动器单元检测到IGBT处于其反向导通状态时，通过其栅电极去激活IGBT或者防止IGBT的激活。

公开(公告)号：US08228113B2

公开(公告)日：2012-07-24

申请号：US12914301

申请日：2010-10-28

Applicant: Daniel Domes

Inventor： Daniel Domes

IPC: H03K17/687

CPC classification number: H03K17/567 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/30107 ,  H03K2017/6875 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A power semiconductor module includes a normally on, controllable first power semiconductor switch including at least one first power semiconductor chip, and a normally off, controllable second power semiconductor switch including at least one second power semiconductor chip. The load paths of the first power semiconductor switch and of the second power semiconductor switch are connected in series. The control terminals of all first power semiconductor chips are permanently electrically conductively connected to a conductor track to which no load terminal of any of the first power semiconductor chips is permanently electrically conductively connected, and to which no load terminal and no control terminal of any of the second power semiconductor chips are permanently electrically conductively connected.

Abstract translation: 功率半导体模块包括通常在可控的第一功率半导体开关，其包括至少一个第一功率半导体芯片和包括至少一个第二功率半导体芯片的常闭可控的第二功率半导体开关。 第一功率半导体开关和第二功率半导体开关的负载路径串联连接。 所有第一功率半导体芯片的控制端子永久地导电地连接到任一第一功率半导体芯片的无负载端子永久地导电连接的导体轨道，并且无负载端子和不具有任何 第二功率半导体芯片永久地导电连接。

公开(公告)号：US20120175780A1

公开(公告)日：2012-07-12

申请号：US13423883

申请日：2012-03-19

Applicant: Patrick Baginski ,  Reinhold Bayerer ,  Holger Ruething ,  Daniel Domes

Inventor： Patrick Baginski ,  Reinhold Bayerer ,  Holger Ruething ,  Daniel Domes

IPC: H01L23/48 ,  H01L21/66

CPC classification number: H01L23/34 ,  H01L23/647 ,  H01L27/0248 ,  H01L29/0696 ,  H01L29/42312 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment provides a semiconductor chip including a semiconductor body and a power semiconductor component integrated therein. The power semiconductor component includes a load electrode zone arranged on a first surface of the semiconductor body, a control electrode zone arranged on the first surface, the control electrode zone being electrically insulated from the load electrode zone, and a resistance track arranged on the load electrode zone and the control electrode zone. The resistance track ensures an electrical connection between the load electrode zone and the control electrode zone.

Abstract translation: 一个实施例提供一种包括半导体本体和集成在其中的功率半导体元件的半导体芯片 功率半导体部件包括布置在半导体主体的第一表面上的负载电极区域，布置在第一表面上的控制电极区域，控制电极区域与负载电极区域电绝缘，以及布置在负载上的电阻轨道 电极区和控制电极区。 电阻轨道确保负载电极区域和控制电极区域之间的电连接。

公开(公告)号：US20100001785A1

公开(公告)日：2010-01-07

申请号：US12168369

申请日：2008-07-07

Applicant: Patrick Baginski ,  Reinhold Bayerer ,  Holger Ruething ,  Daniel Domes

Inventor： Patrick Baginski ,  Reinhold Bayerer ,  Holger Ruething ,  Daniel Domes

IPC: G01K7/16 ,  H01L21/66

CPC classification number: H01L23/34 ,  H01L23/647 ,  H01L27/0248 ,  H01L29/0696 ,  H01L29/42312 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment provides a circuit arrangement integrated in a semiconductor body. At least one power semiconductor component integrated in the semiconductor body and having a control connection and a load connection is provided. A resistance component is thermally coupled to the power semiconductor component and likewise integrated into the semiconductor body and arranged between the control connection and the load connection of the power semiconductor component. The resistance component has a temperature-dependent resistance characteristic curve. A driving and evaluation unit is designed to evaluate the current through the resistance component or the voltage drop across the resistance component and provides a temperature signal dependent thereon.

Abstract translation: 一个实施例提供集成在半导体本体中的电路装置。 提供集成在半导体本体中并且具有控制连接和负载连接的至少一个功率半导体部件。 电阻分量热耦合到功率半导体部件，并且同样集成到半导体本体中并且布置在功率半导体部件的控制连接和负载连接之间。 电阻分量具有温度依赖性电阻特性曲线。 驱动和评估单元被设计为评估通过电阻分量的电流或电阻分量两端的电压降，并提供依赖于其的温度信号。

公开(公告)号：US08478559B2

公开(公告)日：2013-07-02

申请号：US13423883

申请日：2012-03-19

Applicant: Patrick Baginski ,  Reinhold Bayerer ,  Holger Ruething ,  Daniel Domes

Inventor： Patrick Baginski ,  Reinhold Bayerer ,  Holger Ruething ,  Daniel Domes

IPC: G01K1/28 ,  G01K1/26 ,  G01K7/21

CPC classification number: H01L23/34 ,  H01L23/647 ,  H01L27/0248 ,  H01L29/0696 ,  H01L29/42312 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment provides a semiconductor chip including a semiconductor body and a power semiconductor component integrated therein. The power semiconductor component includes a load electrode zone arranged on a first surface of the semiconductor body, a control electrode zone arranged on the first surface, the control electrode zone being electrically insulated from the load electrode zone, and a resistance track arranged on the load electrode zone and the control electrode zone. The resistance track ensures an electrical connection between the load electrode zone and the control electrode zone.

Abstract translation: 一个实施例提供一种包括半导体本体和集成在其中的功率半导体元件的半导体芯片。 功率半导体部件包括布置在半导体主体的第一表面上的负载电极区域，布置在第一表面上的控制电极区域，控制电极区域与负载电极区域电绝缘，以及布置在负载上的电阻轨道 电极区和控制电极区。 电阻轨道确保负载电极区域和控制电极区域之间的电连接。

公开(公告)号：US08471600B2

公开(公告)日：2013-06-25

申请号：US13249604

申请日：2011-09-30

Applicant: Daniel Domes

Inventor： Daniel Domes

IPC: H03K5/153

CPC classification number: H03K17/18 ,  H03K17/13

Abstract: A circuit arrangement includes a reverse conducting transistor having a gate electrode and a load current path between an emitter and collector electrode. The transistor is configured to allow for conducting a load current in a forward direction and in a reverse direction through the load current path and activated or deactivated by a respective signal at the gate electrode. The circuit arrangement further includes a gate control unit and a monitoring unit. The gate control unit is connected to the gate electrode and configured to deactivate the transistor or prevent an activation of the transistor via the gate electrode when the transistor is in a reverse conducting state. The monitoring unit is configured to detect a sudden rise of a collector-emitter voltage of the reverse conducting transistor which occurs, when the load current crosses zero, while the transistor is deactivated or activation is prevented by the gate control unit.

Abstract translation: 电路装置包括具有栅电极和发射极和集电极之间的负载电流路径的反向导通晶体管。 晶体管被配置为允许通过负载电流路径在正向和反向导通负载电流，并且通过栅电极处的相应信号被激活或去激活。 电路装置还包括门控制单元和监视单元。 栅极控制单元连接到栅电极并且被配置为当晶体管处于反向导通状态时，使晶体管停止晶体管或经由栅极电极的激活。 监视单元被配置为检测当负载电流跨越零时发生的反向导通晶体管的集电极 - 发射极电压的突然上升，同时晶体管被禁用或门控制单元的启动被阻止。

公开(公告)号：US20130043593A1

公开(公告)日：2013-02-21

申请号：US13210453

申请日：2011-08-16

Applicant: Daniel Domes

Inventor： Daniel Domes

IPC: H01L23/535

CPC classification number: H01L25/072 ,  H01L23/3735 ,  H01L23/49833 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/29339 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/3011 ,  H02M7/003 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01201 ,  H01L2924/00014

Abstract: A semiconductor arrangement includes a circuit carrier, a bonding wire and at least N half bridge circuits. N is an integer that amounts to at least 1. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each of the half bridge circuits includes a first circuit node, a second circuit node and a third circuit node, a controllable first semiconductor switch and a controllable second semiconductor switch. The controllable first semiconductor switch has a first main contact electrically connected to the first circuit node, a second main contact electrically connected to the third circuit node, and a gate contact for controlling an electric current between the first main contact and the second main contact. Accordingly, the controllable second semiconductor switch has a first main contact electrically connected to the second circuit node, a second main contact electrically connected to the third circuit node, and a gate contact for controlling an electric current between the first main contact and the second main contact. The first semiconductor switch and the second semiconductor switch of each of the half bridge circuits are arranged on that side of the first metallization layer facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer at a first bonding location.

Abstract translation: 半导体装置包括电路载体，接合线和至少N个半桥电路。 N是等于至少为1的整数。电路载体包括第一金属化层，第二金属化层，布置在第一金属化层和第二金属化层之间的中间金属化层，布置在中间金属化层之间的第一绝缘层 层和第二金属化层，以及布置在第一金属化层和中间金属化层之间的第二绝缘层。 半桥电路中的每一个包括第一电路节点，第二电路节点和第三电路节点，可控制的第一半导体开关和可控的第二半导体开关。 可控制的第一半导体开关具有电连接到第一电路节点的第一主触点，与第三电路节点电连接的第二主触头，以及用于控制第一主触点和第二主触点之间的电流的栅极触点。 因此，可控制的第二半导体开关具有电连接到第二电路节点的第一主触头，与第三电路节点电连接的第二主触点，以及用于控制第一主触点和第二主触点之间的电流的栅极触点 联系。 每个半桥电路的第一半导体开关和第二半导体开关被布置在第一金属化层的背离第二绝缘层的一侧。 接合线在第一接合位置处直接接合到中间金属化层。

公开(公告)号：US09106124B2

公开(公告)日：2015-08-11

申请号：US13040348

申请日：2011-03-04

Applicant: Reinhold Bayerer ,  Daniel Domes

Inventor： Reinhold Bayerer ,  Daniel Domes

IPC: H05K7/02 ,  H02M7/00 ,  H01L25/16

CPC classification number: H02M7/003 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A low-inductive power semiconductor assembly is provided in which semiconductor switches are arranged behind one another in a main current path.

Abstract translation: 提供一种低感应功率半导体组件，其中半导体开关在主电流路径中相互布置。