公开(公告)号：US06340630B1

公开(公告)日：2002-01-22

申请号：US09536557

申请日：2000-03-28

申请人： Daniel George Berger ,  Guy Paul Brouillette ,  David Hirsch Danovitch ,  Peter Alfred Gruber ,  Bruce Lee Humphrey ,  Michael Liehr ,  William Thomas Motsiff ,  Carlos Juan Sambucetti

发明人： Daniel George Berger ,  Guy Paul Brouillette ,  David Hirsch Danovitch ,  Peter Alfred Gruber ,  Bruce Lee Humphrey ,  Michael Liehr ,  William Thomas Motsiff ,  Carlos Juan Sambucetti

IPC分类号： A01L2144

CPC分类号： H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11822 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13609 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3468 ,  H05K3/3478 ,  H05K2201/0379 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2224/05647

摘要： A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip. The aligned mold/wafer assembly is then passed through a reflow furnace to effect the transfer of the low melting temperature solder in the mold cavities onto the tip of the high melting temperature solder bumps on the wafer. A dual metallurgical composition bump is thereby formed by the two different solder alloys.

摘要翻译： 可以在能够以低处理温度结合到另一电子设备的电子设备上形成互连的方法可以通过在形成突起的电子设备上沉积第一互连材料，然后沉积第二互连材料至少部分覆盖 所述突起，其中所述第二互连材料具有比所述第一互连材料低的流动温度。 该方法通过将熔融焊料流入具有微腔的模具中以填充空腔，然后使其固化来进行。 然后将模具与包含沉积有高熔点温度焊料凸块的芯片的硅晶片对准，使得模具的每个微腔与芯片上的每个高熔点温度焊料凸块对准。 然后将对准的模具/晶片组件通过回流炉，以将模腔中的低熔点焊料转移到晶片上的高熔点温度焊料凸块的尖端上。 由此由两种不同的焊料合金形成双金属组合物凸块。

公开(公告)号：US6127735A

公开(公告)日：2000-10-03

申请号：US710992

申请日：1996-09-25

申请人： Daniel George Berger ,  Guy Paul Brouillette ,  David Hirsch Danovitch ,  Peter Alfred Gruber ,  Bruce Lee Humphrey ,  Michael Liehr ,  William Thomas Motsiff ,  Carlos Juan Sambucetti

发明人： Daniel George Berger ,  Guy Paul Brouillette ,  David Hirsch Danovitch ,  Peter Alfred Gruber ,  Bruce Lee Humphrey ,  Michael Liehr ,  William Thomas Motsiff ,  Carlos Juan Sambucetti

IPC分类号： B23K35/26 ,  H01L21/60 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/81 ,  H05K3/3436 ,  H05K3/3468 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11822 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13609 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H05K2201/0379 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K3/3463 ,  H05K3/3478 ,  Y02P70/613

摘要： A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip. The aligned mold/wafer assembly is then passed through a reflow furnace to effect the transfer of the low melting temperature solder in the mold cavities onto the tip of the high melting temperature solder bumps on the wafer. A dual metallurgical composition bump is thereby formed by the two different solder alloys.

摘要翻译： 可以在能够以低处理温度结合到另一电子设备的电子设备上形成互连的方法可以通过在形成突起的电子设备上沉积第一互连材料，然后沉积第二互连材料至少部分覆盖 所述突起，其中所述第二互连材料具有比所述第一互连材料低的流动温度。 该方法通过将熔融焊料流入具有微腔的模具中以填充空腔，然后使其固化来进行。 然后将模具与包含沉积有高熔点温度焊料凸块的芯片的硅晶片对准，使得模具的每个微腔与芯片上的每个高熔点温度焊料凸块对准。 然后将对准的模具/晶片组件通过回流炉，以将模腔中的低熔点焊料转移到晶片上的高熔点温度焊料凸块的尖端上。 由此由两种不同的焊料合金形成双金属组合物凸块。

公开(公告)号：US5897336A

公开(公告)日：1999-04-27

申请号：US864196

申请日：1997-05-28

申请人： Guy Paul Brouillette ,  David Hirsch Danovitch ,  Michael Liehr ,  William Thomas Motsiff ,  Judith Marie Roldan ,  Carlos Juan Sambucetti ,  Ravi F. Saraf

发明人： Guy Paul Brouillette ,  David Hirsch Danovitch ,  Michael Liehr ,  William Thomas Motsiff ,  Judith Marie Roldan ,  Carlos Juan Sambucetti ,  Ravi F. Saraf

IPC分类号： H01L21/60 ,  H01L23/556 ,  H05K1/18 ,  H05K3/24 ,  H05K3/32 ,  H05K3/34 ,  H01L21/44

CPC分类号： H01L24/83 ,  H01L23/556 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K3/244 ,  H05K3/321

摘要： An interconnect system that has low alpha particle emission characteristics for use in an electronic device includes a semiconductor chip that has an upper surface and spaced apart electrically resistive bumps positioned on conductive regions of the upper surface, the electrically resistive bumps are made of a composite material of a polymer and metal particles, and a substrate that has conductive regions bonded to the electrically resistive bumps in a bonding process wherein the electrically resistive bumps convert to electrically conductive bumps after the bonding process.

摘要翻译： 具有用于电子设备的低α粒子发射特性的互连系统包括半导体芯片，该半导体芯片具有位于上表面的导电区域上的上表面和间隔开的电阻凸起，电阻凸起由复合材料制成 的聚合物和金属颗粒，以及在接合工艺中具有与电阻凸块接合的导电区域的基板，其中在粘合工艺之后电阻凸块转换为导电凸块。

公开(公告)号：US5731624A

公开(公告)日：1998-03-24

申请号：US671903

申请日：1996-06-28

申请人： William Thomas Motsiff ,  Robert Michael Geffken ,  Ronald Robert Uttecht

发明人： William Thomas Motsiff ,  Robert Michael Geffken ,  Ronald Robert Uttecht

IPC分类号： H01L23/525 ,  H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5258 ,  H01L2924/0002

摘要： A semiconductor interconnection consists of a corrosion resistant integrated fuse and Controlled, Collapse Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non copper fuse material is directly connected to copper wiring.

摘要翻译： 半导体互连由用于平面铜后端（BEOL）的耐腐蚀集成保险丝和受控塌陷芯片连接（C4）结构组成。 非铜保险丝材料直接连接到铜线。

公开(公告)号：US06440834B2

公开(公告)日：2002-08-27

申请号：US09827871

申请日：2001-04-06

申请人： Timothy Harrison Daubenspeck ,  William Thomas Motsiff ,  Jed Hickory Rankin

发明人： Timothy Harrison Daubenspeck ,  William Thomas Motsiff ,  Jed Hickory Rankin

IPC分类号： H01L2144

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.

摘要翻译： 提供一种具有邻接第一和第二导线的导电熔丝材料的半导体熔丝结构。 本发明的保险丝基本上不会损坏周围的半导体材料，所以它可以用于各种各样的材料，包括多孔，机械脆性，低介电常数的材料和诸如Cu的高导电金属。 本文还提供了制造这种半导体熔丝结构的方法。

公开(公告)号：US07704876B2

公开(公告)日：2010-04-27

申请号：US11847657

申请日：2007-08-30

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US07300867B2

公开(公告)日：2007-11-27

申请号：US11174985

申请日：2005-07-05

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）互连结构的方法，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US06958540B2

公开(公告)日：2005-10-25

申请号：US10604026

申请日：2003-06-23

申请人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

发明人： Jeffrey Gambino ,  Edward Cooney, III ,  Anthony Stamper ,  William Thomas Motsiff ,  Michael Lane ,  Andrew Simon

IPC分类号： H01L21/768 ,  H01L23/42 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures are disclosed for forming dual damascene back-end-of-line (BEOL) structure using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.

摘要翻译： 公开了用于形成双镶嵌后端（BEOL）结构的互连结构，其使用与用于线路导体的那些不同的通孔或螺柱的材料，或者使用不同于所使用的通孔衬垫的材料 用于沟槽衬垫，或者具有不同于沟槽衬套的通孔衬垫厚度。 优选地，在通孔中使用厚的难熔金属以改善机械强度，同时仅在沟槽中使用薄的难熔金属来提供低电阻。

公开(公告)号：US06605526B1

公开(公告)日：2003-08-12

申请号：US09527141

申请日：2000-03-16

申请人： Wayne John Howell ,  Ronald Lee Mendelson ,  William Thomas Motsiff ,  Jean-Guy Quintal ,  Sylvain Ouimet

发明人： Wayne John Howell ,  Ronald Lee Mendelson ,  William Thomas Motsiff ,  Jean-Guy Quintal ,  Sylvain Ouimet

IPC分类号： H01L214763

CPC分类号： H01L24/85 ,  H01L21/76838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48639 ,  H01L2224/48647 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/78 ,  H01L2924/00

摘要： A method for forming a wirebond connection to an integrated circuit structure includes forming an insulative structure overlaying a corrosion susceptible metal wiring within the integrated circuit structure, defining a via through the insulative structure above a portion of the corrosion susceptible metal without exposing the portion of the corrosion susceptible metal, and attaching a wirebond material to the portion of the corrosion susceptible metal. The attaching process includes a preliminary process of exposing the portion of the corrosion susceptible metal. The attaching completely covers the portion of the corrosion susceptible metal.

摘要翻译： 用于形成与集成电路结构的引线连接的方法包括形成覆盖集成电路结构内的易腐蚀金属布线的绝缘结构，通过绝缘结构在易腐蚀金属的一部分之上限定通孔，而不暴露部分 腐蚀敏感金属，以及将引线键合材料附着到易腐蚀金属的部分。 附着工艺包括暴露腐蚀敏感金属部分的初步工艺。 附件完全覆盖了易腐蚀金属的部分。

公开(公告)号：US06249038B1

公开(公告)日：2001-06-19

申请号：US09326437

申请日：1999-06-04

申请人： Timothy Harrison Daubenspeck ,  William Thomas Motsiff ,  Jed Hickory Rankin

发明人： Timothy Harrison Daubenspeck ,  William Thomas Motsiff ,  Jed Hickory Rankin

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A semiconductor fuse structure having a conductive fuse material abutting a first and second conductive line is provided. The fuse of the present invention does not substantially damage the surrounding semiconductor material therefore it can be used with a wide variety of materials including porous, mechanically fragile, low dielectric constant materials and high conductive metals like Cu. Methods of fabricating such a semiconductor fuse structure are also provided herein.