公开(公告)号：US20070155048A1

公开(公告)日：2007-07-05

申请号：US11412633

申请日：2006-04-26

申请人： Choon Lee ,  Chin Chong ,  David Corisis

发明人： Choon Lee ,  Chin Chong ,  David Corisis

IPC分类号： H01L21/00 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2224/81

摘要： Methods for packaging microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One aspect of the invention is directed toward a method for packaging a microelectronic device that includes coupling an active side of a microelectronic die to a surface of a support member. The microelectronic die can have a backside opposite the active side, a peripheral side extending at least part way between the active side and the backside, and at least one through-wafer interconnect. The method can further include applying an encapsulant to cover a portion of the surface of the support member so that a portion of the encapsulant is laterally adjacent to the peripheral side, removing material from a backside of the microelectronic die to expose a portion of at least one through-wafer interconnect, and applying a redistribution structure to the backside of the microelectronic die.

摘要翻译： 本文公开了使用这种方法形成的微电子器件和微电子器件的封装方法。 本发明的一个方面涉及一种用于封装微电子器件的方法，该方法包括将微电子管芯的有效侧耦合到支撑构件的表面。 微电子管芯可以具有与有源侧相反的背面，在有源侧和背面之间至少部分延伸的外围侧和至少一个贯通晶片互连。 该方法还可以包括施加密封剂以覆盖支撑构件的表面的一部分，使得密封剂的一部分横向邻近周边侧，从微电子管芯的背面去除材料以暴露至少一部分 一个晶片间互连，并将再分布结构施加到微电子管芯的背面。

公开(公告)号：US20080099931A1

公开(公告)日：2008-05-01

申请号：US11969300

申请日：2008-01-04

申请人： Chin Chong ,  Choon Lee ,  David Corisis

发明人： Chin Chong ,  Choon Lee ,  David Corisis

IPC分类号： H01L23/49 ,  H05K1/11

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.

摘要翻译： 用于安装微电子管芯的基板，在这种基板中形成通孔的方法，以及用于封装微电子器件的方法。 根据本发明的一个实施例的制造基板的方法包括在非导电材料片的第一侧上形成导电迹线，并且从片材的第二面通过非导电材料形成通孔， 导电迹线。 该方法还包括去除非导电材料的一部分以形成穿过通孔的至少一部分延伸的非导电材料的边缘。 在一个实施例中，跨过通孔形成边缘暴露出第二导电迹线的至少一部分，以便随后连接到微电子管芯上的端子。

公开(公告)号：US20070181989A1

公开(公告)日：2007-08-09

申请号：US11414864

申请日：2006-05-01

申请人： David Corisis ,  Chin Chong ,  Choon Lee

发明人： David Corisis ,  Chin Chong ,  Choon Lee

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/053 ,  H01L21/56 ,  H01L21/561 ,  H01L22/10 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06503 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

摘要翻译： 本文公开了堆叠的微电子器件和用于制造这种器件的方法。 在一个实施例中，堆叠的微电子器件组件可以包括包括第一插入器衬底的第一已知的良好封装的微电子器件。 第一管芯和第一穿通管互连件电耦合到第一插入器衬底。 第一壳体至少部分地封装第一装置，使得每个第一互连件的一部分在第一壳体的顶部可接近。 第二已知的良好封装的微电子器件以堆叠配置耦合到第一器件。 第二器件可以包括具有多个第二插入器焊盘的第二插入器衬底和与第二插入器衬底电耦合的第二管芯。 第一互连的暴露部分电耦合到对应的第二插入器焊盘。

公开(公告)号：US20070045834A1

公开(公告)日：2007-03-01

申请号：US11217152

申请日：2005-08-31

申请人： Chin Chong ,  Choon Lee ,  David Corisis

发明人： Chin Chong ,  Choon Lee ,  David Corisis

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.

摘要翻译： 用于安装微电子管芯的基板，在这种基板中形成通孔的方法，以及用于封装微电子器件的方法。 根据本发明的一个实施例的制造基板的方法包括在非导电材料片的第一侧上形成导电迹线，并且从片材的第二面通过非导电材料形成通孔， 导电迹线。 该方法还包括去除非导电材料的一部分以形成穿过通孔的至少一部分延伸的非导电材料的边缘。 在一个实施例中，跨过通孔形成边缘暴露出第二导电迹线的至少一部分，以便随后连接到微电子管芯上的端子。

公开(公告)号：US20070166880A1

公开(公告)日：2007-07-19

申请号：US11726283

申请日：2007-03-21

申请人： David Corisis ,  Chin Chong ,  Choon Lee

发明人： David Corisis ,  Chin Chong ,  Choon Lee

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15183 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods of fabrication of lead frame-based semiconductor device packages including at least one land grid array package. At least one semiconductor die is mounted to an interposer substrate, with bond pads of the semiconductor die connected to terminal pads of the interposer substrate. The terminal pads of the interposer substrate may be electrically connected to both a peripheral array pattern of lands and to a central, two-dimensional array pattern of pads, both array patterns located on the opposing side of the interposer substrate from the at least one semiconductor die. The assembly is overmolded with an encapsulant, leaving the opposing side of the interposer substrate free of encapsulant. Lead fingers of a lead frame superimposed on the opposing side of the interposer substrate are bonded directly to the land grid array lands.

摘要翻译： 包括至少一个焊盘栅格阵列封装的引线框架半导体器件封装的制造方法。 将至少一个半导体管芯安装到插入器衬底上，其中半导体管芯的接合焊盘连接到插入器衬底的端子焊盘。 插入器基板的端子焊盘可以电连接到焊盘的外围阵列图案和焊盘的中心的二维阵列图案，两个阵列图案位于中介层衬底的与至少一个半导体的相对侧上 死。 组件用密封剂包覆成型，留下中介层基板的相对侧不含密封剂。 叠置在插入器基板的相对侧上的引线框架的引线指向栅格阵列阵列直接接合。

公开(公告)号：US20060046537A1

公开(公告)日：2006-03-02

申请号：US10927760

申请日：2004-08-27

申请人： Chin Chong ,  Choon Lee

发明人： Chin Chong ,  Choon Lee

IPC分类号： H01R12/00

CPC分类号： H01R12/526 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09836 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/4922

摘要： Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a dielectric portion having a first surface and a second surface. A first terminal is disposed on the first surface of the dielectric portion for connection to a first electronic component. A second terminal is disposed on the second surface of the dielectric portion for connection to a second electronic component. The apparatus further includes a passage extending through the dielectric portion along a longitudinal axis oriented at an oblique angle relative to the first surface. The passage is at least partially filled with conductive material electrically connecting the first terminal to the second terminal.

公开(公告)号：US20070045796A1

公开(公告)日：2007-03-01

申请号：US11217627

申请日：2005-08-31

申请人： Seng Kim Ye ,  Chin Chong ,  Choon Lee ,  Wang Lee ,  Roslan Said

发明人： Seng Kim Ye ,  Chin Chong ,  Choon Lee ,  Wang Lee ,  Roslan Said

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/00 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/16055 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/0106 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

摘要： Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

摘要翻译： 本文描述了微电子器件，堆叠的微电子器件以及用于制造微电子器件的方法。 在一个实施例中，一组堆叠的微电子器件包括（a）具有第一侧和与第一侧相对的第二侧的第一微电子管芯，（b）附接到第一微电子管芯的第一侧的第一衬底， （c）附接到第一微电子管芯的第二侧的第二衬底，（d）附接到第二衬底的多个电耦合器，（e）耦合到电耦合器的第三衬底，以及 （f）附接到第三基板的第二微电子管芯。 电耦合器被定位成使得至少一些电耦合器在第一微电子管芯内。

公开(公告)号：US20060240687A1

公开(公告)日：2006-10-26

申请号：US11475479

申请日：2006-06-26

申请人： Chin Chong ,  Choon Lee

发明人： Chin Chong ,  Choon Lee

IPC分类号： H01R12/00

CPC分类号： H01R12/526 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09836 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/4921 ,  Y10T29/49211 ,  Y10T29/4922

摘要： Circuit boards, microelectronic devices, and other apparatuses having slanted vias are disclosed herein. In one embodiment, an apparatus for interconnecting electronic components includes a dielectric portion having a first surface and a second surface. A first terminal is disposed on the first surface of the dielectric portion for connection to a first electronic component. A second terminal is disposed on the second surface of the dielectric portion for connection to a second electronic component. The apparatus further includes a passage extending through the dielectric portion along a longitudinal axis oriented at an oblique angle relative to the first surface. The passage is at least partially filled with conductive material electrically connecting the first terminal to the second terminal.

公开(公告)号：US08654673B2

公开(公告)日：2014-02-18

申请号：US13025545

申请日：2011-02-11

申请人： Gaurish R Dalvi ,  Choon Lee ,  Ashish Ranjan

发明人： Gaurish R Dalvi ,  Choon Lee ,  Ashish Ranjan

IPC分类号： H04L12/56

CPC分类号： H04L41/0813 ,  H04L12/462 ,  H04L12/4641 ,  H04L45/48 ,  H04L45/54

摘要： A method may include receiving a reconfiguration to a first Virtual Local Area Network (VLAN)/spanning tree table, where the first VLAN/spanning tree table has a first identifier and is associated with a region of a network; updating the first VLAN/spanning tree table to generate a second VLAN/spanning tree table based on the reconfiguration; determining a second identifier of the second VLAN/spanning tree table; and generating a list of identifiers associated with the region of the network, the list including the first identifier and the second identifier.

摘要翻译： 方法可以包括：接收对第一虚拟局域网（VLAN）/生成树表的重新配置，其中第一VLAN /生成树表具有第一标识符并且与网络的区域相关联; 基于重新配置，更新第一个VLAN /生成树表以生成第二个VLAN /生成树表; 确定第二VLAN /生成树表的第二标识符; 以及生成与所述网络的所述区域相关联的标识符的列表，所述列表包括所述第一标识符和所述第二标识符。

公开(公告)号：US20060092080A1

公开(公告)日：2006-05-04

申请号：US11254432

申请日：2005-10-20

申请人： Choon Lee

发明人： Choon Lee

IPC分类号： H01Q1/38

CPC分类号： H01Q9/0471

摘要： A wireless communication device includes an antenna configured with two conductive elements separated by an insulating medium. One conductive element is a ground plane and the other is a microstrip line. The ground plane is formed with a bend proximate an end. The microstrip line and the ground plane exhibit a characteristic impedance that may vary along the length of the microstrip line. The separation distance of the microstrip line from the ground plane is changed to reduce the resonant frequency of the microstrip line. A second microstrip line with an open end and another end shorted to the ground plane is operative to prevent RF current from flowing on the backside of the ground plane. A backside of the ground plane and the second microstrip line may be covered with a lossy magnetic medium to reduce the near field above the backside of the ground plane.

摘要翻译： 无线通信设备包括配置有由绝缘介质隔开的两个导电元件的天线。 一个导电元件是接地平面，另一个是微带线。 接地平面靠近端部形成弯曲。 微带线和接地平面呈现出沿着微带线的长度可能变化的特征阻抗。 改变微带线与接地面的间隔距离，以减小微带线的谐振频率。 具有开放端和与接地面短路的另一端的第二微带线可操作以防止RF电流在接地平面的背面流动。 接地平面和第二微带线的背面可以用有损磁介质覆盖，以减少接地平面后面的近场。