公开(公告)号：US06483692B2

公开(公告)日：2002-11-19

申请号：US09741302

申请日：2000-12-19

申请人： David G. Figueroa ,  Huong T. Do ,  Jorge Pedro Rodriguez ,  Michael Walk

发明人： David G. Figueroa ,  Huong T. Do ,  Jorge Pedro Rodriguez ,  Michael Walk

IPC分类号： H01G220

CPC分类号： H01G2/065 ,  H01L2924/15311

摘要： A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).

公开(公告)号：US06388207B1

公开(公告)日：2002-05-14

申请号：US09751356

申请日：2000-12-29

申请人： David G. Figueroa ,  Michael Walk ,  Yuan-Liang Li ,  Robert L. Sankman

发明人： David G. Figueroa ,  Michael Walk ,  Yuan-Liang Li ,  Robert L. Sankman

IPC分类号： H01R2368

CPC分类号： H05K1/115 ,  H01L23/49805 ,  H01L23/50 ,  H01L23/5383 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/0263 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09854 ,  H01L2224/05599

摘要： To accommodate the operational and structural requirements of high performance integrated circuits, an integrated circuit package includes conductive trenches that are formed within a substrate. The trenches provide increased current carrying capacity, lower inductance, higher capacitance, and single and/or dual reference planes for signal conductors. Trench structures can be provided at various locations within the substrate, such as adjacent to signal conductors and embedded capacitors, as well as on the substrate periphery to couple the package to a socket. Trenches can be formed by routing, drilling, imprinting, and/or microperforation. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

摘要翻译： 为了适应高性能集成电路的操作和结构要求，集成电路封装包括形成在衬底内的导电沟槽。 沟槽提供增加的载流能力，较低的电感，更高的电容，以及用于信号导体的单和/或双参考平面。 沟槽结构可以设置在衬底内的各个位置，例如与信号导体和嵌入式电容器相邻，以及在衬底周边上以将封装耦合到插座。 可以通过布线，钻孔，压印和/或微穿孔形成沟槽。 还描述了制造方法以及将包装应用于电子组件和电子系统。

公开(公告)号：US06407929B1

公开(公告)日：2002-06-18

申请号：US09606882

申请日：2000-06-29

申请人： Aaron Dean Hale ,  Michael Walk ,  David G. Figueroa ,  Joan K. Vrtis ,  Toshimi Kohmura

发明人： Aaron Dean Hale ,  Michael Walk ,  David G. Figueroa ,  Joan K. Vrtis ,  Toshimi Kohmura

IPC分类号： H05K118

CPC分类号： H01L23/50 ,  H01L23/49822 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/15311 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/0401

摘要： An electronic package (302, FIG. 3) includes one or more capacitors (308) embedded within one or more layers (310) of the package. The embedded capacitors are discrete devices, such as integrated circuit capacitors (FIGS. 17-18) or ceramic capacitors. During the package build-up process, the capacitors are mounted (410, FIG. 4) to a package layer, and a non-conductive layer is applied (412) over the capacitors. When the build-up process is completed, the capacitor's terminals (604, 608, FIG. 6) are electrically connected to the top surface of the package. The embedded capacitor structure can be used in an integrated circuit package (1904, FIG. 19), an interposer (1906), and/or a printed circuit board (1908).

摘要翻译： 电子封装（302，图3）包括嵌入在封装的一个或多个层（310）内的一个或多个电容器（308）。 嵌入式电容器是诸如集成电路电容器（图17-18）或陶瓷电容器的分立器件。 在封装构建过程中，将电容器（图4中的410）安装到封装层，并且在电容器上施加非导电层（412）。 当积聚过程完成时，电容器的端子（604,608，图6）电连接到封装的顶表面。 嵌入式电容器结构可以用于集成电路封装（1904，图19），插入器（1906）和/或印刷电路板（1908）中。

公开(公告)号：US20070056454A1

公开(公告)日：2007-03-15

申请号：US11553828

申请日：2006-10-27

申请人： Michael Walk

发明人： Michael Walk

IPC分类号： B41K1/38

CPC分类号： H05K3/107 ,  B29C33/3842 ,  B29C33/40 ,  B33Y80/00 ,  H05K3/0002 ,  H05K2203/0108

摘要： Numerous embodiments of a method and apparatus for forming an imprinting tool are disclosed. In one embodiment, an apparatus for forming a substrate-imprinting tool comprises a build platform configured to receive material, a first mold formed on the build platform, the first mold having first mold feature surfaces, and a second mold formed on the first mold feature surfaces, wherein at least a portion of the second mold is metalized.

摘要翻译： 公开了用于形成压印工具的方法和装置的许多实施例。 在一个实施例中，一种用于形成衬底压印工具的装置包括构造成接收材料的构建平台，形成在构建平台上的第一模具，第一模具具有第一模具特征表面，以及形成在第一模具特征上的第二模具 表面，其中第二模具的至少一部分被金属化。

公开(公告)号：US06897556B2

公开(公告)日：2005-05-24

申请号：US10657686

申请日：2003-09-08

申请人： Jianqi He ,  Yuan-Liang Li ,  Michael Walk

发明人： Jianqi He ,  Yuan-Liang Li ,  Michael Walk

IPC分类号： H01L23/498 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/50 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/19041

摘要： A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.

摘要翻译： 电路封装可以包括第一导电元件的上表面和第二导电元件。 第一导电元件可以从集成电路管芯的相应导电元件接收输入/输出信号，并且第二导电元件可以从相应的第一导电元件接收第一多个输入/输出信号。 封装的下表面可以包括第三导电元件，第三导电元件用于从第一导电元件中的相应另一个接收第二多个输入/输出信号。

公开(公告)号：US07329946B2

公开(公告)日：2008-02-12

申请号：US11063963

申请日：2005-02-23

申请人： Jianqi He ,  Yuan-Liang Li ,  Michael Walk

发明人： Jianqi He ,  Yuan-Liang Li ,  Michael Walk

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/50 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/19041

摘要： A circuit package may include an upper surface of first conductive elements and second conductive elements. The first conductive elements may receive input/output signals from respective conductive elements of an integrated circuit die, and the second conductive elements may receive a first plurality of the input/output signals from respective ones of the first conductive elements. A lower surface of the package may include third conductive elements, the third conductive elements to receive a second plurality of the input/output signals from respective other ones of the first conductive elements.

摘要翻译： 电路封装可以包括第一导电元件的上表面和第二导电元件。 第一导电元件可以从集成电路管芯的相应导电元件接收输入/输出信号，并且第二导电元件可以从相应的第一导电元件接收第一多个输入/输出信号。 封装的下表面可以包括第三导电元件，第三导电元件用于从第一导电元件中的相应另一个接收第二多个输入/输出信号。

公开(公告)号：US07245001B2

公开(公告)日：2007-07-17

申请号：US10915803

申请日：2004-08-11

申请人： Boyd L. Coomer ,  Michael Walk

发明人： Boyd L. Coomer ,  Michael Walk

IPC分类号： H01L29/40 ,  H01L21/48

CPC分类号： H01L21/4857 ,  H05K3/107 ,  H05K3/386 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/09554 ,  H05K2203/0315 ,  H05K2203/1142 ,  Y10T29/49126 ,  Y10T29/49128

摘要： Adhesive material is applied to a surface of a metallic core layer. The adhesive material is removed from a conductive region of the metallic core layer. A metallic contact is provided over the conductive region of the metallic core layer. The metallic core layer is laminated to an imprinted buildup layer, the buildup layer having a dielectric region and a conductive region, wherein a nonconductive region of the metallic core layer is bonded to the dielectric region of the buildup layer and the conductive region of the metallic core layer is bonded to the conductive region of the imprinted-buildup layer.

摘要翻译： 将粘合材料施加到金属芯层的表面。 从金属芯层的导电区域去除粘合材料。 金属接触件设置在金属芯层的导电区域上。 金属芯层层压到压印堆积层上，积层层具有电介质区域和导电区域，其中金属芯层的非导电区域结合到堆积层的电介质区域和金属芯层的导电区域 芯层结合到印迹堆积层的导电区域。

公开(公告)号：US20050212105A1

公开(公告)日：2005-09-29

申请号：US10807022

申请日：2004-03-23

申请人： Michael Walk

发明人： Michael Walk

IPC分类号： H01L21/56 ,  H01L23/02

CPC分类号： H01L21/563 ,  H01L24/13 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L2224/1148 ,  H01L2224/27003 ,  H01L2224/2711 ,  H01L2224/27438 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/83856 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/00

摘要： A system may include a pre-formed portion of underfill material defining openings. The openings may be configured to pass electrical interconnects for coupling an integrated circuit die to a portion of a substrate.

摘要翻译： 系统可以包括限定开口的底部填充材料的预成形部分。 开口可以被配置为通过用于将集成电路管芯耦合到衬底的一部分的电互连。

公开(公告)号：US07594321B2

公开(公告)日：2009-09-29

申请号：US11853856

申请日：2007-09-12

申请人： Thomas S. Dory ,  Michael Walk

发明人： Thomas S. Dory ,  Michael Walk

IPC分类号： H01K3/10 ,  H05K3/10

CPC分类号： H05K3/107 ,  H05K1/0373 ,  H05K3/0014 ,  H05K3/005 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1189 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A package includes at least one electronic component mounted on a substrate formed through imprinting. In an embodiment, the substrate may comprise conductive traces, vias, and patterns of lands on one or more layers. Conductor features of different geometries may be formed by imprinting them simultaneously on one or both surfaces of an imprintable tape. Fabrication apparatus and methods, as well as application of the imprinted package to an electronic assembly, are also described.

摘要翻译： 封装包括安装在通过压印形成的基板上的至少一个电子部件。 在一个实施例中，衬底可以包括导电迹线，通路和一个或多个层上的焊盘图案。 不同几何形状的导体特征可以通过将它们同时压印在可压印带的一个或两个表面上而形成。 还描述了制造装置和方法，以及将压印包装应用于电子组件。

公开(公告)号：US20060172061A1

公开(公告)日：2006-08-03

申请号：US10456160

申请日：2003-06-05

申请人： Toshimi Kohmura ,  Michael Walk

发明人： Toshimi Kohmura ,  Michael Walk

IPC分类号： B05D5/12

CPC分类号： H05K3/4069 ,  H01L2224/16225 ,  H05K3/005 ,  H05K3/107 ,  H05K3/1258 ,  H05K2203/0108 ,  H05K2203/0191 ,  H05K2203/1189

摘要： Numerous embodiments of a method and apparatus for forming a substrate are disclosed. In one embodiment, a method for substrate fabrication comprises imprinting one or more features on a substrate, depositing a protective layer on a substantial portion of the top surface of the substrate, applying a metal filled paste to at least a portion of the one or more features, removing a substantial portion of the protective layer, and curing the metal filled paste to form one or more conductive structures.

摘要翻译： 公开了用于形成衬底的方法和装置的许多实施例。 在一个实施例中，用于衬底制造的方法包括将一个或多个特征压印在衬底上，在衬底的顶表面的大部分上沉积保护层，将金属填充的糊剂施加到所述一个或多个 特征，去除保护层的大部分，以及固化金属填充的浆料以形成一个或多个导电结构。