公开(公告)号：US09705850B2

公开(公告)日：2017-07-11

申请号：US14216332

申请日：2014-03-17

Applicant: Dijiang Huang ,  Zhijie Wang

Inventor： Dijiang Huang ,  Zhijie Wang

IPC: H04L29/06 ,  H04L9/30 ,  G06F21/62

CPC classification number: H04L63/0428 ,  G06F21/6218 ,  H04L9/3073 ,  H04L63/06 ,  H04L63/102 ,  H04L2209/805

Abstract: A new efficient framework based on a Constant-size Ciphertext Policy Comparative Attribute-Based Encryption (CCP-CABE) approach. CCP-CABE assists lightweight mobile devices and storing privacy-sensitive sensitive data into cloudbased storage by offloading major cryptography-computation overhead into the cloud without exposing data content to the cloud. CCP-CABE extends existing attribute-based data access control solutions by incorporating comparable attributes to incorporate more flexible security access control policies. CCP-CABE generates constant-size ciphertext regardless of the number of involved attributes, which is suitable for mobile devices considering their limited communication and storage capacities.

公开(公告)号：US20150371957A1

公开(公告)日：2015-12-24

申请号：US14555558

申请日：2014-11-26

Applicant: Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

Inventor： Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.

Abstract translation: 半导体晶片具有多级结构，其能够阻止并包含切割期间产生的新生裂纹并且抑制水分渗透到模具的有源区域。 该晶片包括由划线所隔开的芯片区域阵列。 管芯区域包括有源区和围绕有源区的第一环。 第一环的一部分包括低k电介质材料。 第二环包括金属和层间电介质（ILD）材料的交替层叠。 围绕环的虚设金属区域包括堆叠的虚拟金属特征并围绕有源区域。 锯格过程控制（SGPC）特征的规则或不规则交错排列降低了切割时的机械应力。

公开(公告)号：US20150255443A1

公开(公告)日：2015-09-10

申请号：US14552442

申请日：2014-11-24

Applicant: Yanbo Xu ,  Zhijie Wang ,  Fei Zong

Inventor： Yanbo Xu ,  Zhijie Wang ,  Fei Zong

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49572 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/83801 ,  H01L2224/83862 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15157 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

Abstract: A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

Abstract translation: 半导体封装具有引线框和功率管芯。 引线框架具有第一裸片，其具有完全穿过其中形成的空腔。 具有下表面的功率模具安装在第一模板上，使得下表面的第一部分使用无焊模片附着粘合剂附接到第一模板，并且下表面的第二部分， 没有附接到第一模板并且邻接形成在第一模板中的空腔，使得第二部分被暴露。

公开(公告)号：US20120128229A1

公开(公告)日：2012-05-24

申请号：US13293727

申请日：2011-11-10

Applicant: Paul W. Sucro ,  Zhijie Wang ,  Deepak Sood ,  Peter M. Lister

Inventor： Paul W. Sucro ,  Zhijie Wang ,  Deepak Sood ,  Peter M. Lister

IPC: G06K9/00

CPC classification number: H01L24/78 ,  G06T7/0008 ,  G06T7/001 ,  G06T2207/20221 ,  G06T2207/30148 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/78 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method of imaging a feature of a semiconductor device is provided. The method includes the steps of: (a) imaging a first portion of a semiconductor device to form a first imaged portion; (b) imaging a subsequent portion of the semiconductor device to form a subsequent imaged portion; (c) adding the subsequent imaged portion to the first imaged portion to form a combined imaged portion; and (d) comparing the combined imaged portion to a reference image of a feature to determine a level of correlation of the combined imaged portion to the reference image.

Abstract translation: 提供了一种对半导体器件的特征进行成像的方法。 该方法包括以下步骤：（a）对半导体器件的第一部分进行成像以形成第一成像部分; （b）对所述半导体器件的后续部分进行成像以形成随后的成像部分; （c）将随后的成像部分添加到第一成像部分以形成组合的成像部分; 和（d）将组合的成像部分与特征的参考图像进行比较，以确定组合的成像部分与参考图像的相关程度。

公开(公告)号：US20110108967A1

公开(公告)日：2011-05-12

申请号：US12790999

申请日：2010-06-01

Applicant: Zhigang BAI ,  Wei Min Chen ,  Zhijie Wang

Inventor： Zhigang BAI ,  Wei Min Chen ,  Zhijie Wang

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/28

CPC classification number: H01L24/85 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85001 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip grid array package includes a die attach pad and a plurality of connector pads. A semiconductor die is mounted on the die attach pad, the semiconductor die having external connection terminals electrically connected respectively to the connector pads. An encapsulating material encapsulates the die and connector pads. A stud protrudes from each of the connector pads for providing an external electrical contact for the semiconductor chip grid array package. Each of the connector pads and respective studs are formed from an electrically conductive sheet. The connector pads have a thickness of at least 60% of the thickness of the conductive sheet and the respective studs have a thickness of no more than 40% of the thickness of the conductive sheet.

Abstract translation: 半导体芯片栅格阵列封装包括管芯附接焊盘和多个连接器焊盘。 半导体管芯安装在管芯安装焊盘上，半导体管芯具有分别电连接到连接器焊盘的外部连接端子。 封装材料封装管芯和连接器焊盘。 一个螺柱从每个连接器焊盘突出，用于为半导体芯片阵列封装提供外部电接触。 每个连接器焊盘和相应的螺柱由导电片形成。 连接器焊盘的厚度至少为导电片的厚度的60％，并且各个螺柱的厚度不超过导电片的厚度的40％。

公开(公告)号：US20080095497A1

公开(公告)日：2008-04-24

申请号：US11870404

申请日：2007-10-10

Applicant: Xin Simon Luo ,  Pei Chuang Chen ,  Leming Wang ,  Zhijie Wang

Inventor： Xin Simon Luo ,  Pei Chuang Chen ,  Leming Wang ,  Zhijie Wang

IPC: G02B6/32

CPC classification number: G02B6/4204 ,  G02B6/32 ,  G02B6/4212

Abstract: A coupling apparatus includes a lens disposed between a port, such as a photodetector, and a light source, such as a fiber. The lens is aligned such that light emitted from the light source is focused by the lens onto the port. Between the lens and light source and/or lens and port, a low contrast medium is disposed to reduce reflection that could degrade signal strength.

Abstract translation: 耦合装置包括设置在诸如光电检测器的端口和诸如光纤的光源之间的透镜。 镜头对齐，使得从光源发射的光被透镜聚焦到端口上。 在透镜和光源和/或透镜和端口之间，设置低对比度介质以减少可能降低信号强度的反射。

公开(公告)号：US09498898B2

公开(公告)日：2016-11-22

申请号：US14555562

申请日：2014-11-26

Applicant: Zhijie Wang ,  Zhigang Bai ,  Mei Liu ,  Jiyong Niu ,  Zhimei Sun ,  Huchang Zhang

Inventor： Zhijie Wang ,  Zhigang Bai ,  Mei Liu ,  Jiyong Niu ,  Zhimei Sun ,  Huchang Zhang

IPC: B28D7/02 ,  H01L21/67 ,  B28D5/02 ,  B28D1/04

CPC classification number: B28D7/02 ,  B28D1/04 ,  B28D5/022 ,  H01L21/67046 ,  H01L21/67092

Abstract: A cleaning subsystem removes unwanted material, such as glaze, from saw blades used in a semiconductor singulation process. A cleaning module moves radially towards the saw blade and vertically with respect to the plane of the saw blade in order to enable abrasive cleaning blocks of the cleaning module to selectively remove material from either the upper and lower surfaces of the saw blade or the outer edge of the saw blade. The cleaning assembly can remove material from the saw blade at a predetermined time or position during the singulation process or upon detection of load imbalance during the rotation of the saw blade.

Abstract translation: 清洁子系统从用于半导体分离过程的锯片中除去不想要的材料，例如釉料。 清洁模块相对于锯片的平面径向朝向锯片并且垂直移动，以便清洁模块的研磨清洁块能够选择性地从锯片的上表面和下表面或外边缘去除材料 的锯片。 清洁组件可以在切割过程期间的预定时间或位置处或者在锯片旋转期间检测到负载不平衡时从锯片上移除材料。

公开(公告)号：US09406625B2

公开(公告)日：2016-08-02

申请号：US14555558

申请日：2014-11-26

Applicant: Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

Inventor： Zhijie Wang ,  Zhigang Bai ,  Jiyong Niu ,  Dehong Ye ,  Huchang Zhang

IPC: H01L23/544 ,  H01L27/118 ,  H01L41/338 ,  H01L23/00 ,  H01L23/58 ,  H01L21/78 ,  H01L21/66

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.

Abstract translation: 半导体晶片具有多级结构，其能够阻止并包含切割期间产生的新生裂纹并且抑制水分渗透到模具的有源区域。 该晶片包括由划线所隔开的芯片区域阵列。 管芯区域包括有源区和围绕有源区的第一环。 第一环的一部分包括低k电介质材料。 第二环包括金属和层间电介质（ILD）材料的交替层叠。 围绕环的虚设金属区域包括堆叠的虚拟金属特征并围绕有源区域。 锯格过程控制（SGPC）特征的规则或不规则交错排列降低了切割时的机械应力。

公开(公告)号：US09252114B2

公开(公告)日：2016-02-02

申请号：US14551070

申请日：2014-11-23

Applicant: Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

Inventor： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

IPC: H01L23/04 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85401 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.

Abstract translation: 栅极阵列组件由具有嵌入式焊料沉积物的电绝缘材料形成。 每个焊料沉积物的第一部分暴露在绝缘材料的第一表面上，并且每个焊料沉积物的第二部分暴露在绝缘材料的相对表面上。 将半导体管芯安装在绝缘材料的第一表面上，并且将管芯的电极与焊丝连接到焊料沉积物上。 然后用保护性封装材料覆盖管芯，接合线和绝缘材料的第一表面。

公开(公告)号：US20150367529A1

公开(公告)日：2015-12-24

申请号：US14555562

申请日：2014-11-26

Applicant: Zhijie Wang ,  Zhigang Bai ,  Mei Liu ,  Jiyong Niu ,  Zhimei Sun ,  Huchang Zhang

Inventor： Zhijie Wang ,  Zhigang Bai ,  Mei Liu ,  Jiyong Niu ,  Zhimei Sun ,  Huchang Zhang

IPC: B28D7/02 ,  B08B1/04 ,  B28D1/04 ,  H01L21/67 ,  B28D5/02

CPC classification number: B28D7/02 ,  B28D1/04 ,  B28D5/022 ,  H01L21/67046 ,  H01L21/67092

Abstract: A cleaning subsystem removes unwanted material, such as glaze, from saw blades used in a semiconductor singulation process. A cleaning module moves radially towards the saw blade and vertically with respect to the plane of the saw blade in order to enable abrasive cleaning blocks of the cleaning module to selectively remove material from either the upper and lower surfaces of the saw blade or the outer edge of the saw blade. The cleaning assembly can remove material from the saw blade at a predetermined time or position during the singulation process or upon detection of load imbalance during the rotation of the saw blade.

Abstract translation: 清洁子系统从用于半导体分离过程的锯片中除去不想要的材料，例如釉料。 清洁模块相对于锯片的平面径向朝向锯片并且垂直移动，以便清洁模块的研磨清洁块能够选择性地从锯片的上表面和下表面或外边缘去除材料 的锯片。 清洁组件可以在切割过程期间的预定时间或位置处或者在锯片旋转期间检测到负载不平衡时从锯片上移除材料。