公开(公告)号：US20150243586A1

公开(公告)日：2015-08-27

申请号：US14551069

申请日：2014-11-23

申请人： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

发明人： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

IPC分类号： H01L23/495 ,  H01L23/433 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L23/49503 ,  H01L21/56 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49568 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

摘要： A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.

摘要翻译： 通过提供包括具有活性表面的半导体管芯和具有附接的导热衬底的相对安装表面的管芯组件来封装半导体管芯。 模具组件安装在引线框架模具标记的第一表面上，使得导热基板夹在模具标记和半导体管芯之间。 管芯的接合焊盘与接合线电连接以引导框架引线指。 然后，模制化合物封装半导体管芯，接合线和导热衬底。 模具标记的第二表面通过模具化合物暴露。

公开(公告)号：US09214413B2

公开(公告)日：2015-12-15

申请号：US14551069

申请日：2014-11-23

申请人： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

发明人： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

IPC分类号： H01L21/50 ,  H01L23/495 ,  H01L21/56 ,  H01L23/373 ,  H01L23/42

CPC分类号： H01L23/49503 ,  H01L21/56 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49568 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

摘要： A semiconductor die is packaged by providing a die assembly that includes a semiconductor die with an active surface and an opposite mounting surface with an attached thermally conductive substrate. The die assembly is mounted on a first surface of a lead frame die flag so that the thermally conductive substrate is sandwiched between the die flag and the semiconductor die. Bonding pads of the die are electrically connected with bond wires to lead frame lead fingers. A mold compound then encapsulates the semiconductor die, bond wires, and thermally conductive substrate. A second surface of the die flag is exposed through the mold compound.

摘要翻译： 通过提供包括具有活性表面的半导体管芯和具有附接的导热衬底的相对安装表面的管芯组件来封装半导体管芯。 模具组件安装在引线框架模具标记的第一表面上，使得导热基板夹在模具标记和半导体管芯之间。 管芯的接合焊盘与接合线电连接以引导框架引线指。 然后，模制化合物封装半导体管芯，接合线和导热衬底。 模具标记的第二表面通过模具化合物暴露。

公开(公告)号：US09252114B2

公开(公告)日：2016-02-02

申请号：US14551070

申请日：2014-11-23

申请人： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

发明人： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

IPC分类号： H01L23/04 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/17 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85401 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.

摘要翻译： 栅极阵列组件由具有嵌入式焊料沉积物的电绝缘材料形成。 每个焊料沉积物的第一部分暴露在绝缘材料的第一表面上，并且每个焊料沉积物的第二部分暴露在绝缘材料的相对表面上。 将半导体管芯安装在绝缘材料的第一表面上，并且将管芯的电极与焊丝连接到焊料沉积物上。 然后用保护性封装材料覆盖管芯，接合线和绝缘材料的第一表面。

公开(公告)号：US20150243623A1

公开(公告)日：2015-08-27

申请号：US14551070

申请日：2014-11-23

申请人： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

发明人： Zhijie Wang ,  Zhigang Bai ,  Aipeng Shu ,  Yanbo Xu ,  Huchang Zhang ,  Fei Zong

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L21/56

CPC分类号： H01L24/17 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/85401 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material.

摘要翻译： 栅极阵列组件由具有嵌入式焊料沉积物的电绝缘材料形成。 每个焊料沉积物的第一部分暴露在绝缘材料的第一表面上，并且每个焊料沉积物的第二部分暴露在绝缘材料的相对表面上。 将半导体管芯安装在绝缘材料的第一表面上，并且将管芯的电极与焊丝连接到焊料沉积物上。 然后用保护性封装材料覆盖管芯，接合线和绝缘材料的第一表面。

公开(公告)号：US20150255443A1

公开(公告)日：2015-09-10

申请号：US14552442

申请日：2014-11-24

申请人： Yanbo Xu ,  Zhijie Wang ,  Fei Zong

发明人： Yanbo Xu ,  Zhijie Wang ,  Fei Zong

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L25/00

CPC分类号： H01L25/18 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49572 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/83801 ,  H01L2224/83862 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15157 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

摘要： A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

摘要翻译： 半导体封装具有引线框和功率管芯。 引线框架具有第一裸片，其具有完全穿过其中形成的空腔。 具有下表面的功率模具安装在第一模板上，使得下表面的第一部分使用无焊模片附着粘合剂附接到第一模板，并且下表面的第二部分， 没有附接到第一模板并且邻接形成在第一模板中的空腔，使得第二部分被暴露。

公开(公告)号：US09613941B2

公开(公告)日：2017-04-04

申请号：US14552442

申请日：2014-11-24

申请人： Yanbo Xu ,  Zhijie Wang ,  Fei Zong

发明人： Yanbo Xu ,  Zhijie Wang ,  Fei Zong

IPC分类号： H01L23/495 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/18 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49572 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/29011 ,  H01L2224/29013 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/83801 ,  H01L2224/83862 ,  H01L2224/85005 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15157 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/35121 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00

摘要： A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed.

公开(公告)号：US08496158B2

公开(公告)日：2013-07-30

申请号：US13604641

申请日：2012-09-06

申请人： Fei Zong ,  Guoliang Gong ,  Meiquan Huang ,  Hejin Liu

发明人： Fei Zong ,  Guoliang Gong ,  Meiquan Huang ,  Hejin Liu

IPC分类号： B23K31/02

CPC分类号： B23K20/007 ,  B23K31/125 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2224/85 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/859 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/207

摘要： A method for monitoring free air ball (FAB) formation during a wire bonding process includes attaching a dummy bond wire to an unused location on a first surface of a semiconductor chip carrier, extending the dummy bond wire a predetermined distance from the first surface such that a tip of the dummy bond wire is spaced from the first surface, and forming a dummy FAB at the tip of the bond wire. A profile of the dummy FAB is inspected with an imaging unit to identify any defects in the dummy FAB. An alarm is triggered and the wire bonding process is halted if the dummy FAB is defective so that bonding parameters may be adjusted. The wire bonding process is restarted after the bonding parameters have been adjusted.

摘要翻译： 一种用于在引线接合过程中监测自由空气球（FAB）形成的方法包括将虚拟接合线附接到半导体芯片载体的第一表面上的未使用位置，将虚拟接合线从第一表面延伸预定距离，使得 虚拟接合线的尖端与第一表面间隔开，并且在接合线的尖端处形成虚拟FAB。 用成像单元检查虚拟FAB的轮廓以识别虚拟FAB中的任何缺陷。 如果虚拟FAB有缺陷，则触发报警并停止接线过程，从而可以调整接合参数。 接合参数调整后重新开始引线接合处理。

公开(公告)号：US20140103096A1

公开(公告)日：2014-04-17

申请号：US13865185

申请日：2013-04-17

申请人： Hanmin Zhang ,  Qingchun He ,  Liqiang Xu ,  Fei Zong

发明人： Hanmin Zhang ,  Qingchun He ,  Liqiang Xu ,  Fei Zong

IPC分类号： H01L23/00

CPC分类号： H01L24/85 ,  H01L22/12 ,  H01L22/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48456 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/78315 ,  H01L2224/789 ,  H01L2224/78901 ,  H01L2224/85181 ,  H01L2224/859 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A wire bonding machine and a method for testing wire bond connection s using the wire bonding machine. The method includes providing a semiconductor assembly that has a semiconductor die mounted to a substrate, each of which has bonding pads. The method includes bonding a wire to one of the bonding pads to form a first wire bond. A shear force then is applied to the first wire bond. A fault signal is generated when a sensor detects the first wire bond moving during application of the shear force.

摘要翻译： 引线接合机和使用引线接合机测试引线接合连接的方法。 该方法包括提供半导体组件，该半导体组件具有安装到衬底的半导体管芯，每个衬底具有接合焊盘。 该方法包括将导线接合到一个接合焊盘以形成第一引线接合。 然后将剪切力施加到第一线接合。 当传感器检测到在施加剪切力期间移动的第一线接合时，产生故障信号。

公开(公告)号：US20150235969A1

公开(公告)日：2015-08-20

申请号：US14551098

申请日：2014-11-24

申请人： Hanmin Zhang ,  Qingchun He ,  Dehong Ye ,  Fei Zong

发明人： Hanmin Zhang ,  Qingchun He ,  Dehong Ye ,  Fei Zong

IPC分类号： H01L23/00 ,  H01L21/78

CPC分类号： H01L23/562 ,  H01L21/78 ,  H01L22/12 ,  H01L24/05 ,  H01L24/94 ,  H01L2224/033 ,  H01L2224/034 ,  H01L2224/0345 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05564 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor wafer having multiple dies has a partially metallized backside. After wafer dicing, each of the multiple dies has, on its backside, a metallized area surrounded by a peripheral non-metallization ring. The non-metallization ring allows for easier optical inspection of the dies for determining the extent of any backside chipping caused by the wafer dicing. The peripheral non-metallization rings are generated by not metalizing the areas flanking the saw streets of the wafer.

摘要翻译： 具有多个管芯的半导体晶片具有部分金属化的背面。 在晶片切割之后，多个管芯中的每一个在其背面具有被外围非金属化环包围的金属化区域。 非金属化环允许更容易地对模具进行光学检查，以确定由晶片切割引起的任何背面切屑的程度。 周边的非金属化环是通过不使晶片的锯条的两侧的区域金属化而产生的。