公开(公告)号：US4654115A

公开(公告)日：1987-03-31

申请号：US849247

申请日：1986-04-08

申请人： Frank D. Egitto ,  Francis Emmi ,  Walter E. Mlynko ,  Robin A. Susko

发明人： Frank D. Egitto ,  Francis Emmi ,  Walter E. Mlynko ,  Robin A. Susko

IPC分类号： B08B3/08 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H05K3/00 ,  H05K3/08 ,  H05K3/26 ,  H05K3/42 ,  B44C1/22 ,  B29C37/00 ,  C03C15/00 ,  C03C25/06

CPC分类号： H05K3/0055 ,  H05K2203/095

摘要： Contaminant is removed from holes by etching in a gaseous plasma by first removing contaminant from the vicinity of the edges of the hole. Next, a mask is provided in the vicinity of the edges to prevent etching by contacting with a gaseous plasma which is different from the gaseous plasma employed in the first etching step. The holes are then etched in a gaseous plasma to remove contaminant from the interior of the holes in the vicinity of the center of the holes, whereby the mask protects the edges from being etched.

摘要翻译： 通过首先从孔的边缘附近去除污染物，通过在气态等离子体中蚀刻从孔中除去污染物。 接下来，在边缘附近设置掩模，以防止与不同于在第一蚀刻步骤中使用的气态等离子体接触的气体等离子体进行蚀刻。 然后在气体等离子体中蚀刻孔，以从孔的中心附近的孔的内部除去污染物，由此掩模保护边缘不被蚀刻。

公开(公告)号：US5110409A

公开(公告)日：1992-05-05

申请号：US631866

申请日：1990-12-21

申请人： Frank D. Egitto ,  Walter E. Mlynko

发明人： Frank D. Egitto ,  Walter E. Mlynko

IPC分类号： H01L21/311 ,  H05K3/00

CPC分类号： H01L21/31138 ,  H05K3/0017

摘要： Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.

摘要翻译： 通过等离子体蚀刻获得增加的蚀刻速率，其中功率以循环或振荡模式施加。

公开(公告)号：US4985112A

公开(公告)日：1991-01-15

申请号：US12696

申请日：1987-02-09

申请人： Frank D. Egitto ,  Walter E. Mlynko

发明人： Frank D. Egitto ,  Walter E. Mlynko

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H05K3/00

CPC分类号： H01L21/31138 ,  H05K3/0017

摘要： Increased etching rates are obtained by plasma etching wherein the power is applied in a cyclical or oscillating mode.

公开(公告)号：US5972570A

公开(公告)日：1999-10-26

申请号：US895748

申请日：1997-07-17

申请人： James A. Bruce ,  Steven J. Holmes ,  Robert K. Leidy ,  Walter E. Mlynko ,  Edward W. Sengle

发明人： James A. Bruce ,  Steven J. Holmes ,  Robert K. Leidy ,  Walter E. Mlynko ,  Edward W. Sengle

IPC分类号： G03F7/004 ,  G03F1/00 ,  G03F7/095 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762 ,  G03F7/26

CPC分类号： G03F7/70633 ,  G03F7/095 ,  G03F7/2022 ,  G03F7/2024 ,  H01L21/0274 ,  H01L21/762

摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.

公开(公告)号：US5672537A

公开(公告)日：1997-09-30

申请号：US714276

申请日：1996-09-17

申请人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son Van Nguyen

发明人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son Van Nguyen

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/76

CPC分类号： H01L27/10861 ,  H01L21/763 ,  Y10S148/05

摘要： Polysilicon (20) in a trench (21) is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall (26) of the trench (21) closest the beam source. Specifically, when the first side wall (26) is closest the beam source and the second side wall (27) is furthest from the beam source, the polysilicon on the first side wall (26) is almost as high as the first side wall (26), while the polysilicon on the more exposed side wall (27) is considerably lower than the first side wall (26) and approximates the shadow of the first side wall (26) on the second side wall (27) relative to the beam. The polysilicon (20) in the trench (21) may be in the shape of a solid angled block approximating the shadow line from the top of side wall (26) to side wall (27); however, it is preferred that the polysilicon take the form of a conformal layer in trench (21) prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line. Contact is made to the polysilicon (20) using strap (23) that electrically connects the side wall (26) with the polysilicon (20). Strap (23) is sized such that it does not extend to the opposite side wall (27) of trench (21), thereby avoiding short circuits. Having the polysilicon (20) approximate the shadow line of the etch permits narrowing the distance between adjacent straps (23) and (24) in an array without the risk of creating a short circuit.

摘要翻译： 在沟槽（21）中的多晶硅（20）以一定角度蚀刻，以在沟槽内产生具有接近距离光束源的沟槽（21）的侧壁（26）的阴影的形状特征的导体。 具体地说，当第一侧壁（26）最靠近光束源和第二侧壁（27）离光束源最远时，第一侧壁（26）上的多晶硅几乎与第一侧壁（ 而更暴露的侧壁（27）上的多晶硅比第一侧壁（26）低得多，并且相对于光束近似于第二侧壁（27）上的第一侧壁（26）的阴影 。 沟槽（21）中的多晶硅（20）可以是从侧壁（26）的顶部到侧壁（27）近似阴影线的实心角块的形状; 然而，优选的是，多晶硅在蚀刻之前在沟槽（21）中具有保形层的形式，使得多晶硅最终具有接近阴影线的成角度的“U”形。 使用将侧壁（26）与多晶硅（20）电连接的带（23）与多晶硅（20）接触。 带（23）的尺寸使得其不延伸到沟槽（21）的相对侧壁（27），从而避免短路。 使多晶硅（20）近似于蚀刻线的阴影线允许在阵列中使相邻带（23）和（24）之间的距离变窄，而不会产生短路。

公开(公告)号：US5053104A

公开(公告)日：1991-10-01

申请号：US443665

申请日：1989-11-29

申请人： Suryadevara V. Babu ,  Joseph G. Hoffarth ,  Allan R. Knoll ,  Walter E. Mlynko ,  John F. Rembetski ,  Kenneth D. Mack

发明人： Suryadevara V. Babu ,  Joseph G. Hoffarth ,  Allan R. Knoll ,  Walter E. Mlynko ,  John F. Rembetski ,  Kenneth D. Mack

IPC分类号： C09K13/00 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311

CPC分类号： H01L21/02019 ,  C09K13/00 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/31116

摘要： A plasma etching process is disclosed wherein the substrate to be etched is first exposed to an etchant gas containing a volatile organohalide. When the etch rate is stabilized, the organohalide in the etchant gas is replaced by oxygen whereby the etch rate of the substrate is immediately increased to a substantially higher value. When the above is repeatedly done a substantially higher average etch rate is obtained.

摘要翻译： 公开了一种等离子体蚀刻工艺，其中待蚀刻的衬底首先暴露于含有挥发性有机卤化物的蚀刻剂气体。 当蚀刻速率稳定时，蚀刻剂气体中的有机卤化物被氧代替，从而衬底的蚀刻速率立即增加到相当高的值。 当重复上述操作时，获得了显着更高的平均蚀刻速率。

公开(公告)号：US6147394A

公开(公告)日：2000-11-14

申请号：US172366

申请日：1998-10-14

申请人： James A. Bruce ,  Steven J. Holmes ,  Robert K. Leidy ,  Walter E. Mlynko ,  Edward W. Sengle

发明人： James A. Bruce ,  Steven J. Holmes ,  Robert K. Leidy ,  Walter E. Mlynko ,  Edward W. Sengle

IPC分类号： G03F7/004 ,  G03F1/00 ,  G03F7/095 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/762 ,  H01L29/00

CPC分类号： G03F7/70633 ,  G03F7/095 ,  G03F7/2022 ,  G03F7/2024 ,  H01L21/0274 ,  H01L21/762

摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.

摘要翻译： 本发明的优选实施例提供了一种使用单个掩蔽步骤在半导体衬底上限定三个区域的方法。 优选实施例使用光刻胶材料，同时具有曝光的正色调和负色调响应。 这种材料的组合可以提供一种新型的抗蚀剂，我们称之为混合抗蚀剂。 混合抗蚀剂包含作用于第一光化能级的正色调成分和以第二光化能级起作用的负色调成分，其中第一和第二光化能级被光化能的中间范围分隔。 当混合抗蚀剂暴露于光化能时，受到完全曝光的抗蚀剂的区域交联以形成负色调线图案，未曝光形式的区域保持光活性并形成正色调图案，并且暴露于 中间量的辐射在开发过程中变得可溶并被冲走。 这暴露了掩码上的第一个区域。 然后毯子暴露混合抗蚀剂，正色调图案变得可溶，并且在显影过程中将被洗掉。 这掩盖了掩模上的第二区域，第三区域仍被混合抗蚀剂覆盖。 因此，优选实施例能够使用单个掩蔽步骤来定义三个区域，而不会叠加错误。

公开(公告)号：US5610441A

公开(公告)日：1997-03-11

申请号：US444465

申请日：1995-05-19

申请人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son V. Nguyen

发明人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son V. Nguyen

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/18 ,  H01L23/52

CPC分类号： H01L27/10861 ,  H01L21/763 ,  Y10S148/05

摘要： Polysilicon in a trench is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall of the trench closest the beam source. Specifically, when the first side wall is closest to the beam source and the second side wall is furthest from the beam source, the polysilicon on the first side wall is almost as high as the first side wall, while the polysilicon on the more exposed side wall is considerably lower than the first side wall and approximates the shadow of the first side wall on the second side wall relative to the beam. The polysilicon in the trench may be in the shape of a solid angled block approximating the shadow line from the top of side wall to the shadow line on side wall however, it is preferred that the polysilicon take the form of a conformal layer in trench prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line. Contact is made to the polysilicon using strap that electrically connects the side wall with the polysilicon. Strap is sized such that it does not extend to the opposite side wall of trench, thereby avoiding short circuits. Having the polysilicon approximate the shadow line of the etch permits narrowing the distance between adjacent straps and in an array without the risk of creating a short.

摘要翻译： 在沟槽中蚀刻多晶硅以在沟槽内产生导体，该导体具有接近最接近光束源的沟槽侧壁阴影的形状特征。 具体地，当第一侧壁最靠近光束源并且第二侧壁距离光束源最远时，第一侧壁上的多晶硅几乎与第一侧壁一样高，而在较大曝光侧的多晶硅 壁比第一侧壁大得多，并且近似于相对于梁的第二侧壁上的第一侧壁的阴影。 沟槽中的多晶硅可以是接近从侧壁顶部到侧壁上的阴影线的阴影线的实心角形块的形状，然而，优选地，多晶硅在沟槽中具有保形层的形式 以蚀刻，使得多晶硅最终具有近似于阴影线的成角度“U”形。 使用将侧壁与多晶硅电连接的带子与多晶硅接触。 带的尺寸使得其不延伸到沟槽的相对侧壁，从而避免短路。 使多晶硅近似于蚀刻的阴影线允许在相邻带之间和阵列之间的距离变窄，而不会产生短路。

公开(公告)号：US06221775B1

公开(公告)日：2001-04-24

申请号：US09159699

申请日：1998-09-24

申请人： Thomas G. Ference ,  William F. Landers ,  Michael J. MacDonald ,  Walter E. Mlynko ,  Mark P. Murray ,  Kirk D. Peterson

发明人： Thomas G. Ference ,  William F. Landers ,  Michael J. MacDonald ,  Walter E. Mlynko ,  Mark P. Murray ,  Kirk D. Peterson

IPC分类号： H01L21302

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A process of planarizing the surface of a semiconductor substrate. The process begins by forming patterned raised and recessed regions on the surface of the semiconductor substrate. A layer of material then is formed over the patterned raised and recessed regions. The layer is subjected to a chemical mechanical planarizing (CMP) process step until all of the raised regions are at least partially removed from the layer. Finally, the surface of the polished substrate is etched with a reactive ion etching (RIE) process.

摘要翻译： 平面化半导体衬底的表面的工艺。 该过程通过在半导体衬底的表面上形成图案化的凸起和凹陷区域开始。 然后在图案化的凸起和凹陷区域上形成一层材料。 对该层进行化学机械平坦化（CMP）工艺步骤，直到所有凸起区域至少部分地从层中去除。 最后，用反应离子蚀刻（RIE）工艺蚀刻抛光衬底的表面。

公开(公告)号：US5312717A

公开(公告)日：1994-05-17

申请号：US949963

申请日：1992-09-24

申请人： Harbans S. Sachdev ,  John C. Forster ,  Leo L. Linehan ,  Scott A. MacDonald ,  K. Paul L. Muller ,  Walter E. Mlynko ,  Linda K. Somerville

发明人： Harbans S. Sachdev ,  John C. Forster ,  Leo L. Linehan ,  Scott A. MacDonald ,  K. Paul L. Muller ,  Walter E. Mlynko ,  Linda K. Somerville

IPC分类号： G03F7/26 ,  G03F7/36 ,  G03C5/00

CPC分类号： G03F7/36 ,  G03F7/265

摘要： A method for transferring a pattern through a photoresist layer in the fabrication of submicron semiconductor devices structures is disclosed. A photoresist is provided on a substrate and the same is imagewise exposed with a desired pattern to form exposed and unexposed patterned areas in the top surface of the photoresist. The photoresist is then baked to form cross-linked regions in the exposed pattern areas of the photoresist. Silylation is then performed to incorporate silicon into the unexposed patterned areas of the photoresist, wherein some incorporation of silicon occurs in the exposed patterned crosslinked areas of the photoresist. The patterned photoresist is subsequently etched using a high density, low pressure, anisotropic O.sub.2 plasma alone to produce residue-free images with vertical wall profiles in the photoresist. This method is particularly advantageous with RFI reactive ion etch systems.

摘要翻译： 公开了在制造亚微米半导体器件结构中通过光致抗蚀剂层转印图案的方法。 在基板上提供光致抗蚀剂，并将其以所需图案成像曝光，以在光致抗蚀剂的顶表面中形成曝光和未曝光的图案区域。 然后将光致抗蚀剂烘烤以在光致抗蚀剂的暴露图案区域中形成交联区域。 然后进行硅烷化以将硅结合到光致抗蚀剂的未曝光图案区域中，其中硅的一些掺入发生在光致抗蚀剂的暴露的图案化交联区域中。 随后使用高密度，低压，各向异性O 2等离子体蚀刻图案化的光致抗蚀剂，以在光致抗蚀剂中产生具有垂直壁分布的无残留图像。 该方法对于RFI反应离子蚀刻系统是特别有利的。