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    Method for preparing a narrow angle defined trench in a substrate
    1.
    发明授权
    Method for preparing a narrow angle defined trench in a substrate 失效
    在衬底中制备窄角限定沟槽的方法

    公开(公告)号：US5672537A

    公开(公告)日：1997-09-30

    申请号：US714276

    申请日：1996-09-17

    申请人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son Van Nguyen

    发明人： Daniel A. Carl ,  Donald M. Kenney ,  Walter E. Mlynko ,  Son Van Nguyen

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/76

    CPC分类号： H01L27/10861 ,  H01L21/763 ,  Y10S148/05

    摘要： Polysilicon (20) in a trench (21) is etched at an angle to produce a conductor within the trench that has shape characteristics which approximate the shadow of the side wall (26) of the trench (21) closest the beam source. Specifically, when the first side wall (26) is closest the beam source and the second side wall (27) is furthest from the beam source, the polysilicon on the first side wall (26) is almost as high as the first side wall (26), while the polysilicon on the more exposed side wall (27) is considerably lower than the first side wall (26) and approximates the shadow of the first side wall (26) on the second side wall (27) relative to the beam. The polysilicon (20) in the trench (21) may be in the shape of a solid angled block approximating the shadow line from the top of side wall (26) to side wall (27); however, it is preferred that the polysilicon take the form of a conformal layer in trench (21) prior to etching such that the polysilicon ultimately has an angled "U" shape which approximates the shadow line. Contact is made to the polysilicon (20) using strap (23) that electrically connects the side wall (26) with the polysilicon (20). Strap (23) is sized such that it does not extend to the opposite side wall (27) of trench (21), thereby avoiding short circuits. Having the polysilicon (20) approximate the shadow line of the etch permits narrowing the distance between adjacent straps (23) and (24) in an array without the risk of creating a short circuit.

    摘要翻译： 在沟槽（21）中的多晶硅（20）以一定角度蚀刻，以在沟槽内产生具有接近距离光束源的沟槽（21）的侧壁（26）的阴影的形状特征的导体。 具体地说，当第一侧壁（26）最靠近光束源和第二侧壁（27）离光束源最远时，第一侧壁（26）上的多晶硅几乎与第一侧壁（ 而更暴露的侧壁（27）上的多晶硅比第一侧壁（26）低得多，并且相对于光束近似于第二侧壁（27）上的第一侧壁（26）的阴影 。 沟槽（21）中的多晶硅（20）可以是从侧壁（26）的顶部到侧壁（27）近似阴影线的实心角块的形状; 然而，优选的是，多晶硅在蚀刻之前在沟槽（21）中具有保形层的形式，使得多晶硅最终具有接近阴影线的成角度的“U”形。 使用将侧壁（26）与多晶硅（20）电连接的带（23）与多晶硅（20）接触。 带（23）的尺寸使得其不延伸到沟槽（21）的相对侧壁（27），从而避免短路。 使多晶硅（20）近似于蚀刻线的阴影线允许在阵列中使相邻带（23）和（24）之间的距离变窄，而不会产生短路。

    Low temperature plasma oxidation process
    2.
    发明授权
    Low temperature plasma oxidation process 失效
    低温等离子体氧化工艺

    公开(公告)号：US5330935A

    公开(公告)日：1994-07-19

    申请号：US915752

    申请日：1992-07-21

    申请人： David M. Dobuzinsky ,  David L. Harmon ,  Srinandan R Kasi ,  Donald M. Kenney ,  Son Van Nguyen ,  Tue Nguyen ,  Pai-Hung Pan

    发明人： David M. Dobuzinsky ,  David L. Harmon ,  Srinandan R Kasi ,  Donald M. Kenney ,  Son Van Nguyen ,  Tue Nguyen ,  Pai-Hung Pan

    IPC分类号： C23C8/36 ,  H01L21/31 ,  H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/02

    CPC分类号： H01L21/32105 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/31662 ,  Y10S148/118 ,  Y10S257/90

    摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100.ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (

    摘要翻译： 一种在半导体器件的表面上形成薄膜的工艺。 该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1， 在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。 在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。 此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。 该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。 通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。