公开(公告)号：US5854130A

公开(公告)日：1998-12-29

申请号：US864073

申请日：1997-05-28

申请人： Fu-Liang Yang ,  Yin Chen

发明人： Fu-Liang Yang ,  Yin Chen

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/768 ,  H01L21/76801 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method for forming multilevel interconnects in a semiconductor IC device is provided. The method involves a simplified planarization process for planarization of inter-metal dielectrics that allows for easy and cost-effective fabrication of the device. By this method, an insulating layer is formed over a substrate, then a first conductive layer is formed over the insulating layer and which is selectively removed to form conductive interconnects. Subsequently, a dielectric layer is formed over the conductive interconnects. A photoresist layer is then formed and patterned over the dielectric layer by a spin-coating process. An etching process is then conducted on the photoresist layer and the dielectric layer with a 1:1 etching ratio until the photoresist layer is completely removed. At the same moment when the photoresist layer is completely removed, the via holes are formed. The following steps are the same for fabricating the next-level interconnects. In the foregoing method, the spin-coating process allows the photoresist layer to be formed with a flat top surface. In the etching process, the 1:1 etching ratio on the photoresist layer and the dielectric layer allows the underlying dielectric layer to have a flat top surface when the photoresist layer is completely removed. The planarization process is significantly simplified. This allows the manufacturing costs to be significantly reduced.

摘要翻译： 提供了一种在半导体IC器件中形成多层互连的方法。 该方法涉及用于平坦化金属间电介质的简化平面化处理，其允许容易且成本有效地制造器件。 通过这种方法，在衬底上形成绝缘层，然后在绝缘层上形成第一导电层，并且被选择性地去除以形成导电互连。 随后，在导电互连上形成介电层。 然后通过旋涂方法在介电层上形成并图案化光致抗蚀剂层。 然后在光致抗蚀剂层和电介质层上以1：1的蚀刻比进行蚀刻处理，直到光致抗蚀剂层被完全去除。 在光刻胶层完全除去的同时，形成通孔。 以下步骤与制造下一级互连相同。 在上述方法中，旋涂方法允许光致抗蚀剂层形成为平坦的顶表面。 在蚀刻过程中，当光致抗蚀剂层被完全去除时，光致抗蚀剂层和电介质层上的1：1蚀刻比允许下面的介电层具有平坦的顶表面。 平坦化过程显着简化。 这允许制造成本显着降低。

公开(公告)号：USRE45180E1

公开(公告)日：2014-10-07

申请号：US12792373

申请日：2010-06-02

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L21/311 ,  H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/085 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

摘要翻译： 提供了一种用于形成半导体器件的方法和使用该方法制造的器件。 在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。 通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。 沟槽部分地填充有电介质材料。 去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

公开(公告)号：USRE45165E1

公开(公告)日：2014-09-30

申请号：US13372622

申请日：2012-02-14

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yu Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yu Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L29/06 ,  H01L27/085 ,  H01L29/04

CPC分类号： H01L29/1079 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

公开(公告)号：US08618524B2

公开(公告)日：2013-12-31

申请号：US13029436

申请日：2011-02-17

申请人： Chun-Sheng Liang ,  Tzyh-Cheang Lee ,  Fu-Liang Yang

发明人： Chun-Sheng Liang ,  Tzyh-Cheang Lee ,  Fu-Liang Yang

IPC分类号： H01L45/00

CPC分类号： H01L45/12 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1683

摘要： A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.

摘要翻译： 存储器件包括相变元件，该相变元件还包括具有第一晶粒尺寸的第一相变层; 以及在所述第一相变层上的第二相变层。 第一和第二相变层是相变元件的深度区域。 第二相变层具有与第一平均晶粒尺寸不同的第二平均晶粒尺寸。

公开(公告)号：US08288842B2

公开(公告)日：2012-10-16

申请号：US11655008

申请日：2007-01-18

申请人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L23/544 ,  H01L21/301

CPC分类号： H01L21/78 ,  B28D5/00

摘要： A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.

摘要翻译： 一种方法提供用具有金刚石结构的具有基底材料的晶片切割。 晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。 然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。 制造具有一个或多个模具的晶片，其上的至少一个边缘与形成晶片的基底材料的金刚石结构的天然裂解方向成偏移角。 至少一个切割线具有一个或多个保护元件，用于在晶片沿着切割线切割时保护模具不受不期望的开裂。

公开(公告)号：US20120190163A1

公开(公告)日：2012-07-26

申请号：US13107679

申请日：2011-05-13

申请人： Szu-Hung Chen ,  Hung-Min Chen ,  Yu-Sheng Lai ,  Wen-Fa Wu ,  Fu-Liang Yang

发明人： Szu-Hung Chen ,  Hung-Min Chen ,  Yu-Sheng Lai ,  Wen-Fa Wu ,  Fu-Liang Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L29/665 ,  H01L29/7833

摘要： A method for making a dual silicide or germanide semiconductor comprises steps of providing a semiconductor substrate, forming a gate, forming source/drain regions, forming a first silicide, reducing spacers thickness and forming a second silicide. Forming a gate comprises forming an insulating layer over the semiconductor substrate, and forming the gate over the insulating layer. Forming source/drain regions comprises forming lightly doped source/drain regions in the semiconductor substrate adjacent to the insulating layer, forming spacers adjacent to the gate and over part of the lightly doped source/drain regions, and forming heavily doped source/drain regions in the semiconductor substrate. The first silicide is formed on an exposed surface of lightly and heavily doped source/drain regions. The second silicide is formed on an exposed surface of lightly doped source/drain regions. A first germanide and second germanide may replace the first silicide and the second silicide.

摘要翻译： 制造双硅化物或锗化硅半导体的方法包括提供半导体衬底，形成栅极，形成源极/漏极区域，形成第一硅化物，减少间隔物厚度和形成第二硅化物的步骤。 形成栅极包括在半导体衬底上形成绝缘层，并在绝缘层上形成栅极。 形成源极/漏极区域包括在与绝缘层相邻的半导体衬底中形成轻掺杂源极/漏极区域，在栅极和轻掺杂源极/漏极区域的一部分上形成间隔物，并且形成重掺杂的源极/漏极区域 半导体衬底。 第一硅化物形成在轻掺杂和重掺杂的源/漏区的暴露表面上。 第二硅化物形成在轻掺杂源极/漏极区域的暴露表面上。 第一个锗化物和第二个锗化物可以替代第一个硅化物和第二个硅化物。

公开(公告)号：US08154003B2

公开(公告)日：2012-04-10

申请号：US11836593

申请日：2007-08-09

申请人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Tseung-Yuen Tseng ,  Chih-Yang Lin

发明人： Tzyh-Cheang Lee ,  Fu-Liang Yang ,  Tseung-Yuen Tseng ,  Chih-Yang Lin

IPC分类号： H01L45/00

CPC分类号： H01L45/12 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608

摘要： The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide layer provides a constant resistance.

摘要翻译： 本公开提供了一种存储单元。 存储单元包括第一电极，耦合到第一电极的可变电阻材料层，耦合可变电阻材料层的金属氧化物层; 以及耦合到所述金属氧化物层的第二电极。 在一个实施例中，金属氧化物层提供恒定的电阻。

公开(公告)号：US07923759B2

公开(公告)日：2011-04-12

申请号：US11400853

申请日：2006-04-10

申请人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

IPC分类号： H01L29/768

CPC分类号： H01L29/66553 ,  H01L21/28097 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

摘要翻译： 一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。 形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。 这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。 然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。 然后金属层与栅电极反应形成金属栅极。

公开(公告)号：US20100140580A1

公开(公告)日：2010-06-10

申请号：US12703571

申请日：2010-02-10

申请人： Tzyh-Cheang Lee ,  Ming-Yi Yang ,  Fu-Liang Yang ,  Denny Duan-lee Tang

发明人： Tzyh-Cheang Lee ,  Ming-Yi Yang ,  Fu-Liang Yang ,  Denny Duan-lee Tang

IPC分类号： H01L45/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material.

摘要翻译： 提供了相变存储器。 该方法包括在第一电介质层中形成接触塞。 形成第二电介质层，覆盖第一电介质层和形成在其中的沟槽，暴露接触插塞的部分。 在沟槽的表面上形成金属层。 从金属层形成一个或多个加热器，使得每个加热器沿着沟槽的一个或多个侧壁形成，其中加热器沿侧壁的部分不包括相邻侧壁的拐角区域。 沟槽填充有第三电介质层，并且在第三介电层上形成第四电介质层。 在第四电介质层中形成沟槽并填充相变材料。 在相变材料上形成电极。

公开(公告)号：US07585711B2

公开(公告)日：2009-09-08

申请号：US11497586

申请日：2006-08-02

申请人： Hao-Yu Chen ,  Fu-Liang Yang

发明人： Hao-Yu Chen ,  Fu-Liang Yang

IPC分类号： H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78639 ,  H01L29/78654

摘要： A selectively strained MOS device such as selectively strained PMOS device making up an NMOS and PMOS device pair without affecting a strain in the NMOS device the method including providing a semiconductor substrate comprising a lower semiconductor region, an insulator region overlying the lower semiconductor region and an upper semiconductor region overlying the insulator region; patterning the upper semiconductor region and insulator region to form a MOS active region; forming an MOS device comprising a gate structure and a channel region on the MOS active region; and, carrying out an oxidation process to oxidize a portion of the upper semiconductor region to produce a strain in the channel region.

摘要翻译： 选择性应变MOS器件，例如组成NMOS和PMOS器件对的选择性应变PMOS器件对，而不影响NMOS器件中的应变，该方法包括提供包括下半导体区域，覆盖下半导体区域的绝缘体区域和 上半导体区域覆盖绝缘体区域; 图案化上半导体区域和绝缘体区域以形成MOS有源区; 在所述MOS有源区上形成包括栅极结构和沟道区的MOS器件; 并且进行氧化处理以氧化上部半导体区域的一部分以在沟道区域中产生应变。