公开(公告)号：US08957524B2

公开(公告)日：2015-02-17

申请号：US13834058

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Frank Kuechenmeister ,  Jens Paul ,  Kashi Vishwanath Machani

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/1146 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/207 ,  H01L2924/00

Abstract: One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base.

Abstract translation: 本文公开的一个说明性支柱包括导电耦合到集成电路的接合焊盘和包括导体耦合到接合焊盘的基座的支柱，其中基部具有第一横向尺寸，并且导电耦合到基座 ，其中所述上部具有小于所述第一横向尺寸的第二横向尺寸。 本文公开的形成柱的方法包括形成基底，使得其与集成电路产品上的接合焊盘导电耦合，并且在形成基底之后，形成上部，使得其与基底导电耦合。

公开(公告)号：US08829675B2

公开(公告)日：2014-09-09

申请号：US14083962

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Holm Geisler ,  Dirk Breuer

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/66 ,  H01L23/488

CPC classification number: H01L24/14 ,  H01L22/12 ,  H01L22/20 ,  H01L23/488 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/1184 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/742 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2924/3512 ,  Y10T29/53204 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.

Abstract translation: 用于修补柱状凸块的系统包括：柱凸块修复装置，其适于在位于半导体芯片的金属化系统上方的柱凸块中形成多个应变消除凹口。 该系统还包括一个支柱凸块支撑装置，该支柱凸块支撑装置适于在柱形凸起修复装置形成多个应变消除凹口中的每一个时基本上支撑柱形凸块。

公开(公告)号：US20180158745A1

公开(公告)日：2018-06-07

申请号：US15367888

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/26 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/26 ,  H01L21/56 ,  H01L21/76898 ,  H01L22/12 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L2224/4903 ,  H01L2224/94

Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.

公开(公告)号：US20180286773A1

公开(公告)日：2018-10-04

申请号：US15996960

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/26 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L23/522 ,  H01L21/66

Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.

公开(公告)号：US20140264890A1

公开(公告)日：2014-09-18

申请号：US13834058

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dirk Breuer ,  Frank Kuechenmeister ,  Jens Paul ,  Kashi Vishwanath Machani

IPC: H01L23/488 ,  H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/1146 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/207 ,  H01L2924/00

Abstract: One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the base has a first lateral dimension, and an upper portion that is conductively coupled to the base, wherein the upper portion has a second lateral dimension that is less than the first lateral dimension. A method disclosed herein of forming a pillar includes forming a base such that it is conductively coupled to a bond pad on an integrated circuit product and, after forming the base, forming an upper portion such that it is conductively coupled to the base.

Abstract translation: 本文公开的一个说明性支柱包括导电耦合到集成电路的接合焊盘和包括导体耦合到接合焊盘的基座的支柱，其中基部具有第一横向尺寸，并且导电耦合到基座 ，其中所述上部具有小于所述第一横向尺寸的第二横向尺寸。 本文公开的形成柱的方法包括形成基底，使得其与集成电路产品上的接合焊盘导电耦合，并且在形成基底之后，形成上部，使得其与基底导电耦合。

公开(公告)号：US10607947B2

公开(公告)日：2020-03-31

申请号：US15996960

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L23/58

Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.

公开(公告)号：US10340229B2

公开(公告)日：2019-07-02

申请号：US15729774

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Georg Talut

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.

公开(公告)号：US20190109097A1

公开(公告)日：2019-04-11

申请号：US15729774

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Georg Talut

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2924/3512

Abstract: A semiconductor device comprises non-quadrangular metal regions in the last metallization layer and/or non-quadrangular contact pads, wherein, in some illustrative embodiments, an interdigitating lateral configuration may be obtained and/or an overlap of the contact pads with underlying metal regions may be provided. Consequently, mechanical robustness of the contact pads and the passivation material under the underlying interlayer dielectric material may be increased, thereby suppressing crack formation and crack propagation.

公开(公告)号：US10014234B2

公开(公告)日：2018-07-03

申请号：US15367888

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/00 ,  H01L23/26 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L22/12 ,  H01L22/30 ,  H01L23/3107 ,  H01L23/585 ,  H01L2224/4903 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.

公开(公告)号：US20140077368A1

公开(公告)日：2014-03-20

申请号：US14083962

申请日：2013-11-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivian W. Ryan ,  Holm Geisler ,  Dirk Breuer

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L22/12 ,  H01L22/20 ,  H01L23/488 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/1184 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/742 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2924/3512 ,  Y10T29/53204 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A system for repairing pillar bumps includes a pillar bump repair device that is adapted to form a plurality of strain-relieving notches in a pillar bump that is positioned above a metallization system of a semiconductor chip. The system further includes a pillar bump support device that is adapted to substantially support the pillar bump while the pillar bump repair device is forming each of the plurality of strain-relieving notches.

Abstract translation: 用于修补柱状凸块的系统包括：柱凸块修复装置，其适于在位于半导体芯片的金属化系统上方的柱凸块中形成多个应变消除凹口。 该系统还包括一个支柱凸块支撑装置，该支柱凸块支撑装置适于在柱形凸起修复装置形成多个应变消除凹口中的每一个时基本上支撑柱形凸块。