公开(公告)号：US09343300B1

公开(公告)日：2016-05-17

申请号：US14686857

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Michael Hargrove ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/336 ,  H01L21/02 ,  H01L29/66 ,  H01L21/324 ,  H01L29/167 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/225

CPC classification number: H01L29/66636 ,  H01L21/02579 ,  H01L21/02694 ,  H01L21/2251 ,  H01L21/2257 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848

Abstract: The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.

Abstract translation: 本公开涉及在具有含锗沟道区的PMOS晶体管器件的沟道区域和源极/漏极区域之间形成相对突然的结。 在预先形成的源/漏腔之前，在衬层之上的源极/漏极腔中形成外延半导体材料之前形成衬层。 用于衬里层的材料，特别是锗的浓度（如果有的话）相对于沟道区域和外延源/漏极材料中的锗浓度进行调节，使得在退火过程期间，掺杂剂材料（例如 ，硼）在退火工艺期间从源极/漏极区扩散倾向于积聚在衬里层中或其附近。

公开(公告)号：US09312387B2

公开(公告)日：2016-04-12

申请号：US14069955

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Michael Hargrove ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

Abstract: Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Abstract translation: 公开了涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 本文公开的方法和装置包括形成掺杂的硅衬底鳍片，然后在衬底鳍片周围形成硅/锗层。 所述方法和装置还包括使用栅极第一或栅极末端技术在硅/锗层周围形成栅极结构。

公开(公告)号：US09142674B2

公开(公告)日：2015-09-22

申请号：US14176767

申请日：2014-02-10

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanxiang Liu ,  Michael Hargrove ,  Christian Gruensfelder

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7851

Abstract: Fin field-effect transistor devices and methods of forming the fin field-effect transistor devices are provided herein. In an embodiment, a fin field-effect transistor device includes a semiconductor substrate that has a fin. A gate electrode structure overlies the fin. Source and drain halo and/or extension regions and epitaxially-grown source regions and drain regions are formed in the fin and are disposed adjacent to the gate electrode structure. A body contact is disposed on a contact surface of the fin, and the body contact is spaced separately from the halo and/or extension regions and the epitaxially-grown source regions and drain regions.

Abstract translation: 翅片场效应晶体管器件和形成鳍式场效应晶体管器件的方法在本文中提供。 在一个实施例中，鳍状场效应晶体管器件包括具有鳍片的半导体衬底。 栅极电极结构覆盖翅片。 源极和漏极卤素和/或延伸区域和外延生长的源极区域和漏极区域形成在鳍状物中并且邻近栅电极结构设置。 体接触件设置在翅片的接触表面上，并且体接触件与卤素和/或延伸区域和外延生长的源极区域和漏极区域分开地间隔开。

公开(公告)号：US20150255555A1

公开(公告)日：2015-09-10

申请号：US14197686

申请日：2014-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove ,  William J. Taylor, Jr.

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/1054 ,  H01L29/785

Abstract: One illustrative method disclosed herein involves, among other things, forming a first epi semiconductor material on the exposed opposite sidewalls of a fin to thereby define a semiconductor body, performing at least one etching process to remove at least a portion of the substrate portion of the fin positioned between the first epi semiconductor materials positioned on the opposite sidewalls of the fin and to thereby define a back-gate cavity, forming a back-gate insulating material within the back-gate cavity and on the first epi semiconductor materials, forming a back-gate electrode on the back-gate insulation material within the back-gate cavity and forming a gate structure comprised of a gate insulation layer and a gate electrode around the semiconductor bodies.

Abstract translation: 本文公开的一种说明性方法除其他外包括在鳍的暴露的相对侧壁上形成第一外延半导体材料，从而限定半导体本体，执行至少一个蚀刻工艺以去除衬底部分的至少一部分 翅片定位在位于翅片的相对侧壁上的第一外延半导体材料之间，从而限定背栅腔，在背栅腔内和第一外延半导体材料上形成背栅绝缘材料，形成背 在后栅极腔内的背栅极绝缘材料上形成栅极电极，并且形成由半导体本体周围的栅极绝缘层和栅极电极构成的栅极结构。

公开(公告)号：US20150228792A1

公开(公告)日：2015-08-13

申请号：US14175113

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Ruilong Xie ,  Michael Hargrove

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/51 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/778

Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.

Abstract translation: 所公开的一种装置包括围绕翅片的周边表面定位的栅极结构，沟道半导体材料层，其在器件的沟道长度方向上具有轴向长度，其大致对应于位于栅极之间的栅极结构的总宽度 结构并且围绕翅片的外周表面周围，其中沟道半导体材料层的内表面与翅片的外周表面间隔开并且不接触鳍的外周表面。 公开的一种方法尤其涉及在翅片周围形成第一和第二层半导体材料，围绕第二半导体材料形成栅极结构，去除位于侧壁间隔横向外侧的第一和第二半导体层的部分，以及 去除位于第二半导体材料层下方的第一半导体材料层。

公开(公告)号：US20140017862A1

公开(公告)日：2014-01-16

申请号：US14028957

申请日：2013-09-17

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation

Inventor： Jian Yu ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Chengwen Pei ,  Michael Hargrove

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device is provided that includes forming a gate structure on a channel portion of a semiconductor substrate, forming an interlevel dielectric layer over the gate structure, and forming a opening through the interlevel dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source region and the drain region. A metal semiconductor alloy contact is formed on the exposed surface of the semiconductor substrate. At least one dielectric sidewall spacer is formed on sidewalls of the opening. An interconnect is formed within the opening in direct contact with the metal semiconductor alloy contact.

Abstract translation: 提供一种形成半导体器件的方法，包括在半导体衬底的沟道部分上形成栅极结构，在栅极结构上方形成层间电介质层，并通过层间介质层形成通向半导体的暴露表面的开口 含有源区和漏区中的至少一个的衬底。 在半导体衬底的暴露表面上形成金属半导体合金接触。 在开口的侧壁上形成至少一个电介质侧壁间隔物。 在与金属半导体合金接触件直接接触的开口内形成互连。

公开(公告)号：US09318342B2

公开(公告)日：2016-04-19

申请号：US14811987

申请日：2015-07-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/311 ,  H01L21/308 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US20150123166A1

公开(公告)日：2015-05-07

申请号：US14069955

申请日：2013-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Michael Hargrove ,  Ruilong Xie

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

Abstract: are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.

Abstract translation: 是涉及在FinFET器件的沟道区域中形成不同半导体材料的交替层的方法和器件。 本文公开的方法和装置包括形成掺杂的硅衬底鳍片，然后在衬底鳍片周围形成硅/锗层。 所述方法和装置还包括使用栅极第一或栅极末端技术在硅/锗层周围形成栅极结构。

公开(公告)号：US09472554B2

公开(公告)日：2016-10-18

申请号：US13955693

申请日：2013-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Michael Hargrove ,  Yanxiang Liu ,  Christian Gruensfelder

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821

Abstract: Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.

Abstract translation: 本文提供了具有FinFET的集成电路和制造集成电路的方法。 在一个实施例中，制造具有FinFET的集成电路的方法包括提供包括鳍片的衬底。 翅片包括半导体材料。 在翅片的侧壁表面上形成第一金属氧化物层。 第一金属氧化物层包括第一金属氧化物。 第一金属氧化物层凹入到翅片的顶表面下方的深度以形成凹陷的第一金属氧化物层。 翅片顶部的翅片的顶表面和侧壁表面不含第一金属氧化物层。 在翅片顶部的翅片的顶表面和侧壁表面上形成栅电极结构。 凹陷的第一金属氧化物层凹陷在栅电极结构下方。

公开(公告)号：US20160093713A1

公开(公告)日：2016-03-31

申请号：US14963378

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: A transistor device includes a semiconductor substrate and a gate structure positioned above a surface of the semiconductor substrate. The gate structure includes a high-k gate insulation layer positioned above the surface of the semiconductor substrate and at least one work-function adjusting layer of material positioned above the high-k gate insulation layer, wherein an upper surface of the at least one work-function adjusting layer of material has a stepped profile when viewed in cross-section taken in a gate-width direction of the transistor device. The gate structure further includes a layer of conductive material positioned on the stepped upper surface of the at least one work-function adjusting layer of material.

Abstract translation: 晶体管器件包括半导体衬底和位于半导体衬底表面之上的栅极结构。 栅极结构包括位于半导体衬底的表面上方的高k栅极绝缘层和位于高k栅极绝缘层上方的材料的至少一个功函数调节层，其中该至少一个工件的上表面 当在晶体管器件的栅极宽度方向上截取的横截面中观察时，材料的功能调节层具有阶梯形轮廓。 栅极结构还包括位于至少一个功函数调节层材料的阶梯状上表面上的导电材料层。