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公开(公告)号：US20150200111A1
公开(公告)日：2015-07-16
申请号：US14153120
申请日：2014-01-13
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Sruthi Muralidharan , Zhenyu Hu , Qi Zhang , Ja-Hyung Han , Dinesh Koli , Zhuangfei Chen
IPC: H01L21/321 , H01L21/02 , H01L21/265
CPC classification number: H01L21/32115 , H01L21/28035 , H01L21/28123 , H01L21/32137 , H01L29/66545 , H01L29/66795
Abstract: Embodiments of the present invention provide improved methods for fabrication of finFETs. During finFET fabrication, a film, such as amorphous silicon, is deposited on a semiconductor substrate which has regions with fins and regions without fins. A fill layer is deposited on the film and planarized to form a flush surface. A recess or etch process is used to form a planar surface with all portions of the fill layer removed. A finishing process such as a gas cluster ion beam process may be used to further smooth the substrate surface. This results in a film having a very uniform thickness across the structure (e.g. a semiconductor wafer), resulting in improved within-wafer (WiW) uniformity and improved within-chip (WiC) uniformity.
Abstract translation: 本发明的实施例提供了用于制造finFET的改进方法。 在finFET制造期间，诸如非晶硅的膜沉积在半导体衬底上，该半导体衬底具有鳍片和不具有鳍片的区域。 填充层沉积在膜上并且被平坦化以形成齐平表面。 使用凹陷或蚀刻工艺来形成平坦表面，其中填充层的所有部分被去除。 可以使用诸如气体簇离子束工艺的精加工工艺来进一步平滑衬底表面。 这导致在结构（例如半导体晶片）上具有非常均匀的厚度的膜，导致晶片内（WiW）的均匀性提高和芯片内（WiC）均匀性提高。
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公开(公告)号：US10096488B2
公开(公告)日：2018-10-09
申请号：US15608283
申请日：2017-05-30
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Michael Ganz , Bingwu Liu , Johannes Marinus Van Meer , Sruthi Muralidharan
IPC: H01L21/02 , H01L21/266 , H01L29/78 , H01L21/324 , H01L21/3213 , H01L29/66 , H01L21/265 , H01L21/268 , H01L21/3105
Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.
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公开(公告)号：US09293586B2
公开(公告)日：2016-03-22
申请号：US13944048
申请日：2013-07-17
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Zhenyu Hu , Richard J. Carter , Andy Wei , Qi Zhang , Sruthi Muralidharan , Amy L. Child
CPC classification number: H01L29/7848 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/24 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.
Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。
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公开(公告)号：US09219002B2
公开(公告)日：2015-12-22
申请号：US14028724
申请日：2013-09-17
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Zhenyu Hu , Andy Wei , Qi Zhang , Richard J. Carter , Hongliang Shen , Daniel Pham , Sruthi Muralidharan
IPC: H01L21/336 , H01L21/762 , H01L21/308
CPC classification number: H01L21/76224 , H01L21/3081 , H01L21/845 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.
Abstract translation: 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。
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Patent Agency Ranking
公开(公告)号：US20150021695A1
公开(公告)日：2015-01-22
申请号：US13944048
申请日：2013-07-17
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Zhenyu Hu , Richard J. Carter , Andy Wei , Qi Zhang , Sruthi Muralidharan , Amy L. Child
CPC classification number: H01L29/7848 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/24 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.
Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。
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公开(公告)号：US09812336B2
公开(公告)日：2017-11-07
申请号：US14519215
申请日：2014-10-21
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Michael Ganz , Bingwu Liu , Johannes Marinus Van Meer , Sruthi Muralidharan
IPC: H01L21/02 , H01L21/266 , H01L29/78 , H01L21/324 , H01L29/66 , H01L21/265 , H01L21/3213 , H01L21/268
CPC classification number: H01L21/324 , H01L21/0217 , H01L21/0228 , H01L21/265 , H01L21/266 , H01L21/268 , H01L21/31055 , H01L21/32139 , H01L29/66795 , H01L29/66803 , H01L29/7851 , H01L29/7854
Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure. The invention also provides a method of forming a semiconductor structure including: providing an intermediate semiconductor structure having a semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate material disposed over the fin; forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask including an oxide layer; forming a silicon nitride barrier layer on the oxide layer of the gate stack hardmask; performing one or more gate stack hardmask patterning steps; removing the EG oxide layer from portions of the fin that are not located under the gate; and subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.
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公开(公告)号：US09508850B2
公开(公告)日：2016-11-29
申请号：US15012760
申请日：2016-02-01
Applicant: GLOBALFOUNDRIES INC.
Inventor： Zhenyu Hu , Richard J. Carter , Andy Wei , Qi Zhang , Sruthi Muralidharan , Amy L. Child
CPC classification number: H01L29/7848 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/24 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.
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公开(公告)号：US20160163862A1
公开(公告)日：2016-06-09
申请号：US15012760
申请日：2016-02-01
Applicant: GLOBALFOUNDRIES INC.
Inventor： ZHENYU HU , Richard J. Carter , Andy Wei , Qi Zhang , Sruthi Muralidharan , Amy L. Child
CPC classification number: H01L29/7848 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/24 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/785
Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.
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公开(公告)号：US20150076653A1
公开(公告)日：2015-03-19
申请号：US14028724
申请日：2013-09-17
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Zhenyu Hu , Andy Wei , Qi Zhang , Richard J. Carter , Hongliang Shen , Daniel Pham , Sruthi Muralidharan
IPC: H01L21/308 , H01L29/06 , H01L21/762
CPC classification number: H01L21/76224 , H01L21/3081 , H01L21/845 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
Abstract: Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification.
Abstract translation: 提供了用于提高集成电路（IC）设备的覆盖性能的方法。 具体地，IC器件（例如，鳍式场效应晶体管（FinFET））设置有形成在衬底上的氧化物层和衬垫层，其中氧化物层包括取向和覆盖标记，沉积在一组 通过衬垫层并进入衬底形成的开口，沉积在氧化物材料和衬垫层上的心轴层，以及在IC器件中图案化的一组鳍片，而不蚀刻对准和重叠标记。 利用这种方法，对准和重叠标记设置有翅片切割（FC）层，因此避免了精细化。
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