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    Effective biasing active circulator with RF choke concept
    2.
    发明授权
    Effective biasing active circulator with RF choke concept 有权

    公开(公告)号：US09893401B2

    公开(公告)日：2018-02-13

    申请号：US14554995

    申请日：2014-11-26

    Applicant: HRL Laboratories, LLC

    Inventor： Jongchan Kang ,  Hasan Sharifi ,  Eric M. Prophet

    IPC: H01P1/383 ,  H03H11/38

    CPC classification number: H01P1/383 ,  H03H11/16 ,  H03H11/38

    Abstract: A multi-port active circulator where each of a plurality of FET transistors has (i) a gate connected to an associated port of the multi-port active circulator via a capacitor of an associated one of a plurality of first RF chokes, each of the first RF chokes being connected to a gate of an associated FET transistor of said plurality of transistors, the associated port of said associated FET transistor and to a power supply bias connection; (ii) a source connected to a common point; and (iii) a drain connected to the gate of the same FET transistor by a feedback circuit and connected to the gate of a neighboring FET transistor via a capacitor of one of a plurality of second RF chokes, each of which coupling gates and drains of neighboring FET transistors via capacitors thereof and being connected to another power supply bias connection.

    Active circulator with cascode transistor
    5.
    发明授权
    Active circulator with cascode transistor 有权

    公开(公告)号：US09641156B1

    公开(公告)日：2017-05-02

    申请号：US14949044

    申请日：2015-11-23

    Applicant: HRL LABORATORIES, LLC

    Inventor： Jongchan Kang ,  Hasan Sharifi ,  Eric M. Prophet

    IPC: H01P1/32 ,  H03H11/38

    CPC classification number: H03H11/38 ,  H03K17/693

    Abstract: A multi-port active circulator includes a plurality of cascode circuits coupled to one another in a ring. Each respective cascode circuit of the plurality of cascode circuits is coupled to a respective port of a plurality of ports. Each respective cascode circuit includes a common source transistor, a common gate transistor coupled to the common source transistor, and a feedback circuit coupled from the common gate transistor to the common source transistor. Each common source transistor of each respective cascode circuit is coupled to a common junction point.

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