Light emitting compositional semiconductor device
    1.
    发明授权
    Light emitting compositional semiconductor device 失效
    发光组合半导体器件

    公开(公告)号:US5057881A

    公开(公告)日:1991-10-15

    申请号:US444194

    申请日:1989-11-30

    IPC分类号: H01L33/06 H01S5/00 H01S5/34

    CPC分类号: H01L33/06 B82Y20/00 H01S5/34

    摘要: A multiple quantum well light emitting compositional semiconductor device ch as a laser diode or a light emitting diode has an active region comprising an alternating sequence of layers of well layer material and of barrier layer material. The thickness of the barrier layer and of the adjacent well layers is chosen such that for one type of charge carrier a relatively high probability exists for such charge carriers to be present in the barrier region whereas the other type of charge carriers are localized in the potential wells. In this way it is possible to reduce the probability of non-radiative Auger recombination processes occurring thus reducing the threshold current and increasing the quantum efficiency of the device. This is particularly important since material systems with a small bandgap which lase at long wavelengths suitable for optical fibre transmission normally suffer performance penalties due to non-radiative Auger recombination and these penalties can be substantially reduced by tailoring the layer thicknesses to achieve the described probability distributions.

    摘要翻译: 诸如激光二极管或发光二极管的多量子阱发光组合半导体器件具有包括阱层材料层和势垒层材料的交替序列的有源区。 选择阻挡层和相邻阱层的厚度,使得对于一种类型的电荷载体,存在这样的电荷载流子存在于阻挡区域中的相对高的概率,而另一种类型的载流子被定位在电位 井。 以这种方式,可以降低发生的非辐射俄歇复合过程的可能性,从而降低阈值电流并提高器件的量子效率。 这是特别重要的,因为具有适用于光纤传输的长波长的小带隙的材料系统通常由于非辐射俄歇复合而遭受性能惩罚,并且通过调整层厚度可以显着减少这些惩罚以实现所描述的概率分布 。

    Electron-wave coupled semiconductor switching device
    3.
    发明授权
    Electron-wave coupled semiconductor switching device 失效
    电子耦合半导体开关器件

    公开(公告)号:US5148242A

    公开(公告)日:1992-09-15

    申请号:US645064

    申请日:1991-01-22

    CPC分类号: H01L29/772

    摘要: An electron-wave coupled semiconductor device, in particular a semiconductor switching device, comprises a first layer of semiconducting material having a first bandgap, and a second layer of material formed on said first semiconducting layer and having a second bandgap greater than the first said bandgap. First and second electron waveguides are formed alongside but spaced apart from each other in the first semiconductor layer adjacent the boundary between this layer and said second layer. A gate region extends over said second layer transverse to and over said electron waveguides. First contact means provides input connections to said first and second electron waveguides on one side of said gate region and further contact means provides separate output connections from said first and second electron waveguides on the opposite side of the gate region from said first contact means. The dimension of the electron waveguides under said gate region, both along and transverse to said electron waveguides, and also the dimension between said electron waveguides are smaller than the elastic mean free path for electrons at the operating temperature of the device. A signal applied to the gate region can be used to switch a signal applied to said input contact means selectively to a selected one of the output connections.

    摘要翻译: 电子耦合半导体器件,特别是半导体开关器件,包括具有第一带隙的第一半导体材料层和形成在所述第一半导体层上的第二层材料,并且具有大于第一所述带隙的第二带隙 。 第一和第二电子波导在与该层和所述第二层之间的边界相邻的第一半导体层中沿着彼此间隔开形成。 栅极区域横跨所述电子波导的上方延伸超过所述第二层。 第一接触装置提供在所述栅极区域的一侧上与所述第一和第二电子波导的输入连接,并且另外的接触装置在与所述第一接触装置的栅极区域相对的一侧提供与所述第一和第二电子波导的分开的输出连接。 在所述栅极区域下方的电子波导的尺寸,沿着和横向于所述电子波导,以及所述电子波导之间的尺寸小于在器件的工作温度下的电子的弹性平均自由程。 施加到栅极区域的信号可以用于将施加到所述输入触点装置的信号有选择地切换到所选输出连接中的一个。

    Method of preparing semiconductor substrates
    4.
    发明授权
    Method of preparing semiconductor substrates 失效
    半导体衬底的制备方法

    公开(公告)号:US4732648A

    公开(公告)日:1988-03-22

    申请号:US942473

    申请日:1986-12-16

    摘要: A new method for GaAs substrate preparation which significantly reduces theormation of oval defects during MBE growth of selectively doped n-Al.sub.x Ga.sub.1-x As/GaAs heterostructures. The method simply requires treatment in H.sub.2 SO.sub.4 after mechano-chemical polishing in NaOCl solution and generation of a protective surface oxide during in soldering. Routinely a density of oval defects of less than 200 cm.sup.-2 is achieved for 2-.mu.m thick heterostructures. The efficiency of the new preparation procedure is demonstrated by 2DEG mobilities in excess of 10.sup.6 cm.sup.2 /Vs at 6K obtained with a spacer width as narrow as 18 nm.

    摘要翻译: 一种用于GaAs衬底制备的新方法,其在选择性掺杂的n-Al x Ga 1-x As / GaAs异质结构的MBE生长期间显着减少椭圆形缺陷的形成。 该方法只需要在NaOCl溶液中机械化学抛光后在H2SO4中进行处理,并在焊接过程中产生保护性表面氧化物。 实际上,对于2μm厚的异质结构,实现小于200cm-2的椭圆形缺陷的密度。 新的制备方法的效率通过在6K处超过106cm 2 / Vs的2DEG迁移率证明,其间隔宽度窄至18nm。

    Magnetic logic device
    7.
    发明申请
    Magnetic logic device 失效
    磁逻辑器件

    公开(公告)号:US20060164124A1

    公开(公告)日:2006-07-27

    申请号:US10536699

    申请日:2003-11-26

    IPC分类号: H03K19/20

    CPC分类号: H03K19/18

    摘要: A method for operating a magnetic logic device (10) is described wherein at least one output variable O=F (IA, IB) is formed from input variables (IA, IB) by at least one logic operation with an operator function F of the magnetic logic device (10), whereby the logic device (10) is set at a starting state for executing the operator function F with a certain operator control signal (SET) before the operation, whereby the operator control signal is selected from a group of control signals with which various non-volatile starting states can be set in a controlled manner, each state being characteristic of a different logic function. Furthermore, a magnetic logic device (10) equipped for implementation of this method is also described.

    摘要翻译: 描述了一种用于操作磁逻辑器件(10)的方法,其中至少一个输出变量O = F(I A,I B B)由输入变量(I 通过具有磁逻辑器件(10)的操作器功能F的至少一个逻辑运算,由此将逻辑器件(10)设置在一个或多个逻辑器件(10) 用于在操作之前用一定的操作员控制信号(SET)执行操作功能F的起动状态,从而从可以以受控的方式设置各种非易失性起动状态的一组控制信号中选择操作员控制信号, 每个状态是不同逻辑功能的特征。 此外,还描述了配备用于实现该方法的磁逻辑装置(10)。

    Method of generating active semiconductor structures by means of
starting structures which have a 2D charge carrier layer parallel to
the surface
    8.
    发明授权
    Method of generating active semiconductor structures by means of starting structures which have a 2D charge carrier layer parallel to the surface 失效
    通过具有平行于表面的2D电荷载体层的起始结构产生有源半导体结构的方法

    公开(公告)号:US5338692A

    公开(公告)日:1994-08-16

    申请号:US93971

    申请日:1993-05-03

    摘要: A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another. The source and drain are only connected by a narrow channel 44 the width of which is continuously tunable by a gate potential which is simultaneously applied to the two gate regions relative to the source, so that a pronounced change of the carrier concentration and thus of the channel resistance arises. The specification also describes integrated circuits made using the same methods.

    摘要翻译: 提出了具有FET的所有特性的准一维载流子通道的单极电子元件。 该部件可以非常简单地制造,具有“自对准”和具有低容量的线性门来代替平面栅极。 以这种方式,组件的非常高的工作频率是可能的。 该结构包括通过例如GaAs的外延形成的具有高载流子迁移率的初始均匀的2D层。 聚焦离子(例如Ga +与100keV)的注入会局部地破坏电子层的导电性。 即使在用带隙辐射照射碎片之后,照射区域在低温或室温下保持绝缘。 绝缘层的写入沿着芯片上的两条路径进行,使得2D载体层被细分成彼此绝缘的三个区域。 源极和漏极仅由窄通道44连接,窄通道44的宽度可通过栅极电位连续可调,该栅极电位同时施加到相对于源极的两个栅极区域,使得载流子浓度明显变化 通道电阻出现。 本说明书还描述了使用相同方法制造的集成电路。

    Method of generating active semiconductor structures by means of
starting structures which have a 2D charge carrier layer parallel to
the surface
    10.
    发明授权
    Method of generating active semiconductor structures by means of starting structures which have a 2D charge carrier layer parallel to the surface 失效
    通过具有平行于表面的2D电荷载体层的起始结构产生有源半导体结构的方法

    公开(公告)号:US5396089A

    公开(公告)日:1995-03-07

    申请号:US34315

    申请日:1993-03-22

    摘要: A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another. The source and drain are only connected by a narrow channel 44 the width of which is continuously tunable by a gate potential which is simultaneously applied to the two gate regions relative to the source, so that a pronounced change of the carrier concentration and thus of the channel resistance arises. The specification also describes integrated circuits made using the same methods.

    摘要翻译: 提出了具有FET的所有特性的准一维载流子通道的单极电子元件。 该部件可以非常简单地制造,具有“自对准”和具有低容量的线性门来代替平面栅极。 以这种方式,组件的非常高的工作频率是可能的。 该结构包括通过例如GaAs的外延形成的具有高载流子迁移率的初始均匀的2D层。 聚焦离子(例如Ga +与100keV)的注入会局部地破坏电子层的导电性。 即使在用带隙辐射照射碎片之后,照射区域在低温或室温下保持绝缘。 绝缘层的写入沿着芯片上的两条路径进行,使得2D载体层被细分成彼此绝缘的三个区域。 源极和漏极仅由窄通道44连接,窄通道44的宽度可通过栅极电位连续可调,该栅极电位同时施加到相对于源极的两个栅极区域,使得载流子浓度明显变化 通道电阻出现。 本说明书还描述了使用相同方法制造的集成电路。