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    Trench storage capacitor
    1.
    发明申请
    Trench storage capacitor 审中-公开
    沟槽存储电容

    公开(公告)号：US20070034927A1

    公开(公告)日：2007-02-15

    申请号：US11272038

    申请日：2005-11-14

    申请人： Harald Seidl ,  Dirk Manger ,  Matthias Goldbach ,  Albert Birner ,  Stefan Slesazeck

    发明人： Harald Seidl ,  Dirk Manger ,  Matthias Goldbach ,  Albert Birner ,  Stefan Slesazeck

    IPC分类号： H01L29/94

    CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/945

    摘要： A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a “buried” collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

    摘要翻译： 沟槽存储电容器包括一掩埋板，其被掺杂的硅层延伸到芯套绝缘层的正上方。 沟槽存储电容器的导体层优选地应用于“埋入”的轴环绝缘层，并借助于由ALD制成的保护层进行掩模。 在示例性实施例中，导体层由非晶硅组成，其被用作下沟槽区域中的HSG层。

    Memory cell array and method of manufacturing the same
    3.
    发明授权
    Memory cell array and method of manufacturing the same 有权
    存储单元阵列及其制造方法

    公开(公告)号：US07473952B2

    公开(公告)日：2009-01-06

    申请号：US11118768

    申请日：2005-05-02

    申请人： Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

    发明人： Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10876 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891

    摘要： A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

    摘要翻译： 存储单元阵列包括其中形成有多个存储单元的多个有效区域。 存储单元包括存储电容器，至少部分地形成在具有衬底表面的半导体衬底中的晶体管，所述晶体管包括第一源极/漏极区域。 与衬底表面相邻形成的第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道区域。 第一源极/漏极区域邻近于衬底表面形成。 沟道区设置在半导体衬底和栅电极中。 有源区域的行通过沿着第一方向延伸的隔离槽相互分离。 第一和第二字线被布置在每行活动区域的任一侧面上。 第一和第二字线经由相应行的有效区域的晶体管的栅电极相互连接。

    Memory cell array and method of manufacturing the same
    4.
    发明申请
    Memory cell array and method of manufacturing the same 有权

    公开(公告)号：US20060244024A1

    公开(公告)日：2006-11-02

    申请号：US11118768

    申请日：2005-05-02

    申请人： Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

    发明人： Dirk Manger ,  Stefan Slesazeck ,  Stefan Tegen ,  Klaus Muemmler ,  Alexander Sieck

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10876 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891

    摘要： A memory cell array includes a plurality of active areas in which a plurality of memory cells are formed. A memory cell includes a storage capacitor, a transistor at least partially formed in a semiconductor substrate with a substrate surface, the transistor including a first source/drain region. A second source/drain region being formed adjacent to the substrate surface, a channel region connecting the first and second source/drain regions. The first source/drain region is formed adjacent to the substrate surface. The channel region is disposed in the semiconductor substrate, and a gate electrode. Rows of the active areas are separated from each other by isolation grooves that extend along a first direction. A first and a second word lines are disposed on either lateral sides of each of the rows of active areas. The first and the second word lines are connected with each other via the gate electrodes of the transistors of the corresponding row of active areas.

    Method for forming a hard mask in a layer on a planar device
    5.
    发明授权
    Method for forming a hard mask in a layer on a planar device 有权
    在平面装置上的层中形成硬掩模的方法

    公开(公告)号：US07005240B2

    公开(公告)日：2006-02-28

    申请号：US10370857

    申请日：2003-02-20

    申请人： Dirk Manger ,  Matthias Goldbach

    发明人： Dirk Manger ,  Matthias Goldbach

    IPC分类号： G03C5/00

    CPC分类号： H01L21/0337

    摘要： A hard mask is produced from spacer structures. The spacer structures are formed from a conformal deposition on elevated structures produced lithographically in a projection process. The conformal deposition is etched back laterally on the elevated structures resulting in the spacer structures. The elevated structures between the spacer structures are subsequently etched away, so that the spacer structures remain in an isolated fashion as sublithographic structures of a hard mask with a doubled structure density compared with that originally produced in lithographic projection. In a regularly disposed two-dimensional array of structures in the hard mask for forming trenches—for instance for trench capacitors—the method achieves a doubling of the structure density in the array. A further iteration step is formed by forming further spacer structures on the first and second spacer structures, thereby achieving an even higher increase in structure density in the hard mask.

    摘要翻译： 由间隔结构产生硬掩模。 间隔结构由在投影过程中光刻生成的升高结构上的共形沉积形成。 在升高的结构上横向蚀刻共形沉积物，导致间隔物结构。 间隔结构之间的升高的结构随后被蚀刻掉，使得间隔结构保持隔离的方式作为具有双重结构密度的硬掩模的亚光刻结构，与原始在光刻投影中产生的结合密度相比较。 在用于形成沟槽的硬掩模中的例如用于沟槽电容器的规则排列的二维结构阵列中，该方法实现阵列中结构密度的加倍。 通过在第一和第二间隔结构上形成另外的间隔结构形成另外的迭代步骤，从而在硬掩模中实现甚至更高的结构密度增加。

    Method of fabricating a semiconductor device
    7.
    发明授权
    Method of fabricating a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07825031B2

    公开(公告)日：2010-11-02

    申请号：US11855809

    申请日：2007-09-14

    申请人： Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

    发明人： Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

    IPC分类号： H01L21/302

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816

    摘要： The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.

    摘要翻译： 本发明涉及一种制造集成电路的方法，包括提供至少一层的步骤; 执行第一注入步骤，其中在第一入射方向上将颗粒注入所述层中; 执行第二注入步骤，其中在与所述第一入射方向不同的第二入射方向上将颗粒注入所述层中; 执行去除步骤，其中根据由第一和第二植入步骤产生的局部植入剂量部分去除该层。

    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM
    9.
    发明申请
    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
    具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法

    公开(公告)号：US20050088895A1

    公开(公告)日：2005-04-28

    申请号：US10897687

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    IPC分类号： G11C11/34

    CPC分类号： H01L27/10841 ,  H01L27/10867

    摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.

    摘要翻译： 在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。 通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏​​极电容的减小以及栅电极和漏极电极之间的漏电流 较低的源极/漏极区域。 施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构 单元晶体管。