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公开(公告)号：US20130154073A1
公开(公告)日：2013-06-20
申请号：US13327032
申请日：2011-12-15
IPC分类号： H01L23/495 , H01L21/50 , H01L21/28
CPC分类号： H01L23/49524 , H01L23/3107 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L2224/37147 , H01L2224/376 , H01L2224/40095 , H01L2224/40139 , H01L2224/40245 , H01L2224/48137 , H01L2224/49171 , H01L2224/73221 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/84
摘要： In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.
摘要翻译： 在一个实施例中，用于半导体封装的引线框架包括用于一个晶体管的源极连接区域和用于第二晶体管的漏极连接点，以及用于使用连接夹将第一晶体管的漏极耦合到第二晶体管的源极的公共连接 第二晶体管和公共连接。
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公开(公告)号：US08581416B2
公开(公告)日：2013-11-12
申请号：US13327032
申请日：2011-12-15
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/495 , H01L21/00
CPC分类号： H01L23/49524 , H01L23/3107 , H01L23/49575 , H01L24/37 , H01L24/40 , H01L2224/37147 , H01L2224/376 , H01L2224/40095 , H01L2224/40139 , H01L2224/40245 , H01L2224/48137 , H01L2224/49171 , H01L2224/73221 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/84
摘要： In one embodiment, a leadframe for a semiconductor package includes a source connection area for one transistor and a drain connection point for a second transistor, and a common connection for using a connection clip to couple a drain of the first transistor to a source of the second transistor and to the common connection.
摘要翻译： 在一个实施例中，用于半导体封装的引线框架包括用于一个晶体管的源极连接区域和用于第二晶体管的漏极连接点，以及用于使用连接夹将第一晶体管的漏极耦合到第二晶体管的源极的公共连接 第二晶体管和公共连接。
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公开(公告)号：US08461670B2
公开(公告)日：2013-06-11
申请号：US12827980
申请日：2010-06-30
IPC分类号： H01L23/495 , H01L23/48 , H01L21/50
CPC分类号： H01L23/49537 , H01L23/4952 , H01L23/49524 , H01L23/49541 , H01L23/49575 , H01L24/04 , H01L24/06 , H01L24/32 , H01L24/40 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/072 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/32245 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48091 , H01L2224/48137 , H01L2224/48157 , H01L2224/48247 , H01L2224/49111 , H01L2224/49171 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2924/00014 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/19107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099 , H01L2224/84
摘要： A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component is configured to permit the determination of circuit parameters. A high side FET has a gate terminal coupled to an output terminal of a high side gate drive circuit, a drain terminal coupled for receiving an input voltage, and a source terminal coupled to the drain terminal of a low side FET. The gate terminal of the low side FET is coupled to the output terminal of low side drive circuit and the source terminal of the low side FET is coupled for receiving a source of operating potential. The high side gate drive circuit has a bias terminal coupled for receiving a floating potential where the bias terminal is electrically isolated or decoupled from the commonly connected source and drain terminals of the high side FET and the low side FET, respectively.
摘要翻译： 一种半导体元件和半导体元件的制造方法，其中，所述半导体元件被配置为允许确定电路参数。 高侧FET具有耦合到高侧栅极驱动电路的输出端子的栅极端子，耦合用于接收输入电压的漏极端子和耦合到低侧FET的漏极端子的源极端子。 低侧FET的栅极端子耦合到低侧驱动电路的输出端子，并且低侧FET的源极端子被耦合以接收工作电位源。 高侧栅极驱动电路具有耦合用于接收浮置电位的偏置端子，其中偏置端子分别与高侧FET和低侧FET的共同连接的源极和漏极端子电隔离或去耦合。
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公开(公告)号：US20100187663A1
公开(公告)日：2010-07-29
申请号：US12362142
申请日：2009-01-29
IPC分类号： H01L21/60 , H01L23/495
CPC分类号： H01L23/49582 , H01L21/561 , H01L23/3107 , H01L23/495 , H01L23/49541 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/05554 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19107 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.
摘要翻译： 具有可润湿引线框引线表面的半导体部件和制造方法。 具有引线框引线的引线框架嵌入模具化合物中。 至少一个引线框引线的一部分被暴露，并且在暴露部分上形成导电材料。 分离模具化合物以形成单个半导体组分。
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公开(公告)号：US07202106B2
公开(公告)日：2007-04-10
申请号：US10877327
申请日：2004-06-28
申请人： Francis J. Carney , Phillip Celaya , Joseph K. Fauty , James P. Letterman , Stephen St. Germain , Jay A. Yoder
发明人： Francis J. Carney , Phillip Celaya , Joseph K. Fauty , James P. Letterman , Stephen St. Germain , Jay A. Yoder
CPC分类号： H01L23/49575 , H01L2924/0002 , H01L2924/00
摘要： In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
摘要翻译： 在一个示例性实施例中，多芯片连接器被形成为具有适于附接到第一半导体管芯的第一导电条和适于附接到第二半导体管芯的第二导电条。
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6.发明申请SEMICONDUCTOR PACKAGE STRUCTURE HAVING MULTIPLE HEAT DISSIPATION PATHS AND METHOD OF MANUFACTURE 有权具有多个散热片的半导体封装结构及其制造方法公开(公告)号：US20080054438A1
公开(公告)日：2008-03-06
申请号：US11468542
申请日：2006-08-30
IPC分类号： H01L23/48
CPC分类号： H01L23/49568 , H01L23/4334 , H01L23/49548 , H01L23/49562 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： In one embodiment, a semiconductor package structure includes a conductive bridge having coupling portions on opposing ends. A lead frame includes alignment or receiving features for receiving the coupling portions of the bridge. A semiconductor device is attached to both the conductive bridge and the lead frame, and is configured so that the coupling portions are on opposing sides of the semiconductor device.
摘要翻译： 在一个实施例中，半导体封装结构包括具有在相对端上的耦合部分的导电桥。 引线框架包括用于接收桥接件的联接部分的对准或接收特征。 半导体器件附着到导电桥和引线框架上，并且被配置为使得耦合部分在半导体器件的相对侧上。
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公开(公告)号：US20080054424A1
公开(公告)日：2008-03-06
申请号：US11469239
申请日：2006-08-31
申请人： Phillip Celaya , James P. Letterman
发明人： Phillip Celaya , James P. Letterman
IPC分类号： H01L23/02
CPC分类号： H01L23/3107 , H01L23/57 , H01L24/48 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H05K1/0275 , H05K1/181 , H05K2201/09781 , H05K2201/10689 , Y02P70/611 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.
摘要翻译： 在一个实施例中，半导体封装被形成为包括位于半导体封装的至少一部分连接端子和半导体封装的边缘之间的防盗屏障。
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公开(公告)号：US07298034B2
公开(公告)日：2007-11-20
申请号：US10877325
申请日：2004-06-28
申请人： Francis J. Carney , Phillip Celaya , Joseph K. Fauty , James P. Letterman , Stephen St. Germain , Jay A. Yoder
发明人： Francis J. Carney , Phillip Celaya , Joseph K. Fauty , James P. Letterman , Stephen St. Germain , Jay A. Yoder
IPC分类号： H01L23/02
CPC分类号： H01L25/18 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L24/36 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L25/074 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/49109 , H01L2224/73221 , H01L2224/83801 , H01L2224/8385 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012 , H01L2224/37099
摘要： In one exemplary embodiment, a multi-chip semiconductor connector is utilized for forming a semiconductor package having a plurality of semiconductor die. The multi-chip semiconductor connector is utilized to mechanically attach the plurality of semiconductor die together and to provide electrical connection to the plurality of semiconductor die.
摘要翻译： 在一个示例性实施例中，多芯片半导体连接器用于形成具有多个半导体管芯的半导体封装。 多芯片半导体连接器用于将多个半导体管芯机械地附接在一起并提供与多个半导体管芯的电连接。
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公开(公告)号：US20070126107A1
公开(公告)日：2007-06-07
申请号：US11673942
申请日：2007-02-12
申请人： Francis Carney , Phillip Celaya , Joseph Fauty , James Letterman , Stephen Germain , Jay Yoder
发明人： Francis Carney , Phillip Celaya , Joseph Fauty , James Letterman , Stephen Germain , Jay Yoder
IPC分类号： H01L23/02
CPC分类号： H01L25/074 , H01L23/49575 , H01L2924/0002 , H01L2924/13055 , H01L2924/00
摘要： In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is attached to a first semiconductor die and a second conductive strip that is attached to a second semiconductor die.
摘要翻译： 在一个示例性实施例中，多芯片连接器被形成为具有附接到第一半导体管芯的第一导电条和附接到第二半导体管芯的第二导电条。
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公开(公告)号：US20140239472A1
公开(公告)日：2014-08-28
申请号：US13780070
申请日：2013-02-28
申请人： Frank Tim Jones , Phillip Celaya
发明人： Frank Tim Jones , Phillip Celaya
IPC分类号： H01L23/495 , H01L21/82
CPC分类号： H01L23/49551 , H01L23/295 , H01L23/3107 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/0603 , H01L2224/29101 , H01L2224/2929 , H01L2224/32245 , H01L2224/45014 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48111 , H01L2224/48137 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/4903 , H01L2224/49111 , H01L2224/73265 , H01L2225/06562 , H01L2924/0781 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/0665 , H01L2924/014 , H01L2924/00012 , H01L2224/32145 , H01L2224/00
摘要： In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags.
摘要翻译： 在一个实施例中，半导体封装包括第一和第二管芯标记，其中第一和第二管芯标记由间隙分开。 第一和第二金属氧化物半导体场效应晶体管（MOSFET）管芯分别在第一和第二管芯标记上。 功率控制集成电路（IC）堆叠在第一或第二MOSFET管芯中的至少一个的顶部上。 模具化合物封装了功率控制IC，第一和第二MOSFET管芯以及第一和第二管芯标记。
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