公开(公告)号：US4498054A

公开(公告)日：1985-02-05

申请号：US526822

申请日：1983-08-26

申请人： Hirokazu Fukuda ,  Masaru Hashimoto

发明人： Hirokazu Fukuda ,  Masaru Hashimoto

IPC分类号： H03F3/181 ,  H03F3/45 ,  H03G1/00 ,  H03G1/04

CPC分类号： H03F3/4521 ,  H03F3/45071 ,  H03G1/0023 ,  H03G1/04 ,  H03F2203/45366

摘要： A differential amplifier circuit includes first and second differential amplifiers, with respective first input terminals thereof connected to each other and first and second current sources for supplying first and second drive currents to drive the first and second amplifiers respectively. The first and second drive currents are set such that their sum is constant. The differential amplifier circuit further includes first and second transistors with the bases thereof connected to second input terminals of the first and second amplifiers respectively and third and fourth current sources respectively connected to the current paths of the first and second transistors and supplying third and fourth drive currents equal to one half the respective second and first drive currents.

摘要翻译： 差分放大器电路包括第一和第二差分放大器，其相应的第一输入端彼此连接，第一和第二电流源用于提供第一和第二驱动电流以分别驱动第一和第二放大器。 第一和第二驱动电流被设置为使得它们的和是恒定的。 差分放大器电路还包括第一和第二晶体管，其基极分别连接到第一和第二放大器的第二输入端，第三和第四电流源分别连接到第一和第二晶体管的电流路径，并提供第三和第四驱动 相当于相应的第二和第一驱动电流的一半的电流。

公开(公告)号：US08105883B2

公开(公告)日：2012-01-31

申请号：US12568486

申请日：2009-09-28

申请人： Shigeharu Yoshiba ,  Hirokazu Fukuda

发明人： Shigeharu Yoshiba ,  Hirokazu Fukuda

IPC分类号： H01L21/56

CPC分类号： H01L21/565 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Provided is a method for manufacturing a semiconductor device in which movement of an island in resin sealing is prevented. A molding die includes an upper die and a lower die. The upper and lower dies are fitted together to form cavities and runners. In the lower die, a pod is provided. After heating and melting of a tablet made of a solid resin and housed in the pod, the melted sealing resin is pressurized by a plunger, and is supplied to each of the cavities. Specifically, a liquid sealing resin is supplied from the pod to the cavities, sequentially, from the upstream of the flow of the sealing resin supplied from the pod. The cavities communicate with each other through the runners. Furthermore, the runners through which the cavities communicate are provided to be tilted with respect to a path for supplying the sealing resin.

摘要翻译： 提供了一种制造半导体器件的方法，其中防止树脂密封中的岛的移动。 模具包括上模和下模。 上模和下模被装配在一起以形成空腔和流道。 在下模中，提供一个荚。 在由固体树脂制成的片剂加热熔融并容纳在容器中之后，熔融的密封树脂被柱塞加压，并被供应到每个空腔。 具体地说，液体密封树脂从从容器供应的密封树脂的流动的上游顺序地从容器供应到空腔。 空腔通过流道相互连通。 此外，空腔连通的流道被设置成相对于供给密封树脂的路径倾斜。

公开(公告)号：US20050029588A1

公开(公告)日：2005-02-10

申请号：US10941183

申请日：2004-09-15

申请人： Noriaki Sakamoto ,  Yoshiyuki Kobayashi ,  Hirokazu Fukuda ,  Hiroki Etou ,  Kouji Takahashi

发明人： Noriaki Sakamoto ,  Yoshiyuki Kobayashi ,  Hirokazu Fukuda ,  Hiroki Etou ,  Kouji Takahashi

IPC分类号： H01L27/04 ,  H01L21/48 ,  H01L21/822 ,  H01L23/31 ,  H01L23/49 ,  H01L23/58 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET, and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

摘要翻译： 使用MOSFET的保护电路装置具有多个电气分离的导电路径，将芯片中的两个功率MOSFET集成在一个芯片中的MOSFET芯片，其中栅电极和源电极固定在期望的导电路径上，设置在公共漏极上的导电材料 的MOSFET，以及覆盖所述MOSFET的绝缘树脂，并且将所述导电路径支撑在一个主体中。 除去公共漏电极的附近并将源电极直接固定在导电路径上，实现低导通状态电阻。

公开(公告)号：US20050017339A1

公开(公告)日：2005-01-27

申请号：US10869551

申请日：2004-06-15

申请人： Shigeharu Yoshiba ,  Hirokazu Fukuda ,  Haruhiko Sakai

发明人： Shigeharu Yoshiba ,  Hirokazu Fukuda ,  Haruhiko Sakai

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L27/04 ,  H01L29/72 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L29/7813 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12035 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.

摘要翻译： 传统的单芯片双MOSFET具有两个芯片并排布置并且漏电极短路的结构。 因此，其安装面积大，漏电极之间的电阻不能降低。 因此，市场要求的半导体器件的尺寸和厚度的减小是极限的。 该实施例的双MOSFET包括彼此重叠的两个半导体芯片（MOSFET），其漏电极彼此直接连接。 在双MOSFET中，漏电极不需要被引导到外部，并且仅使用两个栅极端子和两个源极端子。 因此，这四个端子通过引线框或导电图案引出。 这使得器件的尺寸减小并具有较低的导通电阻。

公开(公告)号：US20080203582A1

公开(公告)日：2008-08-28

申请号：US11861697

申请日：2007-09-26

申请人： Hideyuki Inotsume ,  Hirokazu Fukuda

发明人： Hideyuki Inotsume ,  Hirokazu Fukuda

IPC分类号： H01L23/52

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device having a plurality of semiconductor chips mounted on lead frames is miniaturized by reducing its planar size and thickness. By disposing a rear surface of a first island and a top surface of a second island so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

摘要翻译： 具有安装在引线框架上的多个半导体芯片的半导体器件通过减小其平面尺寸和厚度而被小型化。 通过将第一岛的后表面和第二岛的顶表面设置为至少部分地彼此重叠，在第一岛上的第一半导体芯片和第二岛的后表面上的第二半导体芯片被配置 以便彼此重叠。 因此，平面占用面积可以设定为小于两个芯片的平面面积。 此外，要连接到第二半导体芯片的细金属线延伸到背面。 因此，也可以减小半导体器件的厚度。

公开(公告)号：US07030501B2

公开(公告)日：2006-04-18

申请号：US10869551

申请日：2004-06-15

申请人： Shigeharu Yoshiba ,  Hirokazu Fukuda ,  Haruhiko Sakai

发明人： Shigeharu Yoshiba ,  Hirokazu Fukuda ,  Haruhiko Sakai

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L29/7813 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12035 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.

摘要翻译： 传统的单芯片双MOSFET具有两个芯片并排布置并且漏电极短路的结构。 因此，其安装面积大，漏电极之间的电阻不能降低。 因此，市场要求的半导体器件的尺寸和厚度的减小是有限的。 该实施例的双MOSFET包括彼此重叠的两个半导体芯片（MOSFET），其漏电极彼此直接连接。 在双MOSFET中，漏电极不需要被引导到外部，并且仅使用两个栅极端子和两个源极端子。 因此，这四个端子通过引线框或导电图案引出。 这使得器件的尺寸减小并具有较低的导通电阻。

公开(公告)号：US4413343A

公开(公告)日：1983-11-01

申请号：US236611

申请日：1981-02-20

申请人： Hirokazu Fukuda ,  Koji Shinohara ,  Mitiharu Itou

发明人： Hirokazu Fukuda ,  Koji Shinohara ,  Mitiharu Itou

IPC分类号： H01L21/28 ,  H01L21/40 ,  H01L29/43 ,  H01L29/45 ,  H01L33/28 ,  H01L33/40 ,  H01L33/62 ,  H01S5/00 ,  H01S5/02 ,  H01S5/30 ,  H01S3/19

CPC分类号： H01L33/40 ,  H01L21/40 ,  H01L29/45 ,  H01S5/02 ,  H01S5/30 ,  H01L33/26

摘要： In lead chalcogenide semiconductor devices such as PbSSe diode lasers, an element which functions as the acceptor, selected from among the elements forming the relevant semiconductor body, added to gold and the combination is used as the p conductivity type region ohmic contact electrode. Stable continuous wave operation in the infrared region is provided by forming the p conductivity type region ohmic contact electrode for the PbSSe diode laser of a AuSe alloy.

摘要翻译： 在诸如PbSSe二极管激光器的铅硫族化物半导体器件中，用作作为受体的元素，从构成相关半导体器件的元素中选出，添加到金中并将其组合用作p导电型区域欧姆接触电极。 通过形成用于AuSe合金的PbSSe二极管激光器的p导电型区域欧姆接触电极来提供红外区域中的稳定的连续波操作。

公开(公告)号：US07535087B2

公开(公告)日：2009-05-19

申请号：US11692563

申请日：2007-03-28

申请人： Hideyuki Inotsume ,  Hirokazu Fukuda

发明人： Hideyuki Inotsume ,  Hirokazu Fukuda

IPC分类号： H01L23/02 ,  H01L23/48

CPC分类号： H01L23/49537 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

摘要翻译： 通过将第一岛12的后表面和第二岛13的顶表面设置为至少部分地彼此重叠，第一岛上的第一半导体芯片和第二岛的后表面上的第二半导体芯片 被配置为彼此重叠。 因此，平面占用面积可以设定为小于两个芯片的平面面积。 此外，要连接到第二半导体芯片20的细金属线延伸到背面。 因此，也可以减小半导体器件的厚度。

公开(公告)号：US07211868B2

公开(公告)日：2007-05-01

申请号：US09809856

申请日：2001-03-16

申请人： Noriaki Sakamoto ,  Yoshiyuki Kobayashi ,  Hirokazu Fukuda ,  Hiroki Etou ,  Kouji Takahashi

发明人： Noriaki Sakamoto ,  Yoshiyuki Kobayashi ,  Hirokazu Fukuda ,  Hiroki Etou ,  Kouji Takahashi

IPC分类号： H01L23/62

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A protection circuit device using a MOSFET has a plural of conductive paths separated electrically, a MOSFET chip integrating two power MOSFETs in one chip where a gate electrode and a source electrode are fixed on the desired conductive path, conductive material provided on a common drain electrode of the MOSFET, and insulating resin covering said MOSFET and supporting said conductive path in one body. Removing a drawing-around of the common drain electrode and fixing the source electrode directly on the conductive path, low ON-state resistance is realized.

摘要翻译： 使用MOSFET的保护电路装置具有多个电气分离的导电路径，将芯片中的两个功率MOSFET集成在一个芯片中的MOSFET芯片，其中栅电极和源电极固定在期望的导电路径上，设置在公共漏极上的导电材料 的MOSFET，以及覆盖所述MOSFET并且将所述导电路径支撑在一个主体中的绝缘树脂。 除去公共漏电极的附近并将源电极直接固定在导电路径上，实现低导通状态电阻。

公开(公告)号：US06545364B2

公开(公告)日：2003-04-08

申请号：US09810110

申请日：2001-03-16

申请人： Noriaki Sakamoto ,  Yoshiyuki Kobayashi ,  Junji Sakamoto ,  Shigeaki Mashimo ,  Katsumi Okawa ,  Eiju Maehara ,  Kouji Takahashi ,  Hirokazu Fukuda ,  Hiroki Etou

发明人： Noriaki Sakamoto ,  Yoshiyuki Kobayashi ,  Junji Sakamoto ,  Shigeaki Mashimo ,  Katsumi Okawa ,  Eiju Maehara ,  Kouji Takahashi ,  Hirokazu Fukuda ,  Hiroki Etou

IPC分类号： H01L2348

CPC分类号： H01L24/40 ,  H01L21/4821 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/06 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： After a trench 54 is formed in a conductive foil 60, a circuit element is mounted in a flip chip method. Then, an insulating resin 50 is covered on the conductive foil 60 as a support substrate. After reversion, the conductive foil 60 is polished over the insulating resin 50 as a support substrate at this time to separate the conductive paths. Accordingly, a circuit device having the conductive paths 51 and the circuit elements 52 supported by the insulating resin 50 can be produced without employing the support substrate.