Semiconductor device and it's manufacturing method
    9.
    发明授权
    Semiconductor device and it's manufacturing method 有权
    半导体器件及其制造方法

    公开(公告)号:US07087956B2

    公开(公告)日:2006-08-08

    申请号:US10203776

    申请日:2001-12-13

    申请人: Taku Umebayashi

    发明人: Taku Umebayashi

    IPC分类号: H01L29/94

    摘要: In a semiconductor device having a memory element and a logic element formed on the same semiconductor substrate, a transistor of the memory element comprises a gate electrode (16) embedded within a trench (13) formed in a semiconductor substrate (11) through a gate insulating film (15) and a diffusion layer (17) formed on the side of the semiconductor substrate (11) at a sidewall of the trench (13), and a take-out electrode (20) connected to the diffusion layer (17) is provided so that the take-out electrode overlaps the gate electrode (16) through a first interlayer insulating film (insulating film) (18) on the gate electrode (16). A word line (16) is provided in the trench (13) and an impurity concentration of the diffusion layer (17) is decreased as a depth thereof is increased.

    摘要翻译: 在具有形成在同一半导体衬底上的存储元件和逻辑元件的半导体器件中,存储元件的晶体管包括嵌入在通过栅极形成在半导体衬底(11)中的沟槽(13)内的栅电极(16) 在所述沟槽(13)的侧壁形成在所述半导体衬底(11)侧的绝缘膜(15)和扩散层(17),以及连接到所述扩散层(17)的取出电极(20) 被提供为使得取出电极通过栅电极(16)上的第一层间绝缘膜(绝缘膜)(18)与栅电极(16)重叠。 在沟槽(13)中设置字线(16),随着​​其深度增加,扩散层(17)的杂质浓度降低。

    SOI SRAM device structure with increased W and full depletion
    10.
    发明授权
    SOI SRAM device structure with increased W and full depletion 失效
    SOI SRAM器件结构增加了W和完全耗尽

    公开(公告)号:US07297577B2

    公开(公告)日:2007-11-20

    申请号:US11027853

    申请日:2004-12-30

    申请人: Taku Umebayashi

    发明人: Taku Umebayashi

    IPC分类号: H01L21/84

    摘要: An SOI device, and a method for producing the SOI device, for use in an SRAM memory having enhanced stability. The SRAM is formed with a wider W and a fully-depleted FET. The wider FET is extended by an expitaxial silicon sidewall, and the performance of the FET is improved.

    摘要翻译: 一种SOI器件,以及用于制造SOI器件的方法,用于具有增强的稳定性的SRAM存储器中。 SRAM形成有较宽的W和完全耗尽的FET。 更宽的FET通过外延硅侧壁延伸,并且FET的性能得到改善。