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    Field-effect transistor and method of manufacturing the same
    1.
    发明授权
    Field-effect transistor and method of manufacturing the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US07642567B2

    公开(公告)日：2010-01-05

    申请号：US11689527

    申请日：2007-03-22

    申请人： Hirotaka Amasuga ,  Masahiro Totsuka

    发明人： Hirotaka Amasuga ,  Masahiro Totsuka

    IPC分类号： H01L29/00

    CPC分类号： H01L29/7787 ,  H01L29/0649

    摘要： A low-cost field-effect transistor with a moisture-resistant gate covered by a thick moisture-resistant insulating film which suppresses an increase in gate capacitance, and a method of manufacturing the field-effect transistor. The field-effect transistor has one of a T-shaped gate electrode and Γ-shaped gate electrode, a drain electrode, and a source electrode, the source electrode and the drain electrode being electrically connected through an n-doped semiconductor region. The gate, source, and drain electrodes are located on a semiconductor layer which includes an insulating film having a thickness of 50 nm or less and covering a surface of the gate electrode and a surface of the semiconductor layer. A silicon nitride film, deposited by catalytic CVD, covers the insulating film and includes a void volume located between a portion of the gate electrode corresponding to a canopy of an open umbrella and the semiconductor layer.

    摘要翻译： 一种具有防潮门的低成本场效应晶体管，其由耐湿绝缘膜覆盖，其抑制栅极电容的增加，以及制造场效应晶体管的方法。 场效应晶体管具有T形栅电极和伽马形栅电极，漏电极和源电极之一，源电极和漏电极通过n掺杂半导体区域电连接。 栅极，源极和漏极位于包括厚度为50nm以下的绝缘膜的半导体层上，并且覆盖栅电极的表面和半导体层的表面。 通过催化CVD沉积的氮化硅膜覆盖绝缘膜，并且包括位于与开放伞的顶盖对应的栅电极的一部分与半导体层之间的空隙体积。

    Semiconductor device including field effect transistor with reduced electric field concentration
    3.
    发明授权
    Semiconductor device including field effect transistor with reduced electric field concentration 有权
    包括具有降低的电场浓度的场效应晶体管的半导体器件

    公开(公告)号：US08232609B2

    公开(公告)日：2012-07-31

    申请号：US12828328

    申请日：2010-07-01

    申请人： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

    发明人： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

    IPC分类号： H01L29/76

    CPC分类号： H01L29/4238 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/812

    摘要： A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.

    摘要翻译： 半导体器件包括：半导体衬底; 在所述半导体衬底的顶表面处的杂质掺杂区域; 绝缘区域，位于半导体衬底的顶表面上的杂质掺杂区域周围; 杂质掺杂区上的栅电极; 位于所述杂质掺杂区域上的第一电极和第二电极，夹着所述栅电极; 位于所述绝缘区域上并连接到所述栅电极的第一焊盘; 在所述绝缘区域上跨越所述杂质掺杂区域面对所述第一焊盘的第二焊盘，并且连接到所述第二电极; 以及位于所述绝缘区域上的所述第一电极和所述第二焊盘之间的导体。

    Cascode circuit
    4.
    发明授权
    Cascode circuit 有权
    串联电路

    公开(公告)号：US07342453B2

    公开(公告)日：2008-03-11

    申请号：US11446201

    申请日：2006-06-05

    申请人： Hirotaka Amasuga ,  Takayuki Matsuzuka ,  Akira Inoue

    发明人： Hirotaka Amasuga ,  Takayuki Matsuzuka ,  Akira Inoue

    IPC分类号： H03F3/16 ,  H03F1/22

    CPC分类号： H03F1/223 ,  H01L27/0222 ,  H01L27/0629 ,  H03F3/195 ,  H03F2200/451 ,  H03F2200/75

    摘要： A cascode circuit in which two field effect transistors (“FET”) are connected in cascode has a first FET having its source grounded, a second FET having its source connected to the drain of the first FET, and a Schottky barrier diode having an anode connected to the source of the first FET and a cathode connected to the gate of the second FET.

    摘要翻译： 其中两个场效应晶体管（“FET”）以共源共栅连接的共源共栅电路具有其源极接地的第一FET，其源极连接到第一FET的漏极的第二FET和具有阳极的肖特基势垒二极管 连接到第一FET的源极和连接到第二FET的栅极的阴极。

    Semiconductor device and method of manufacturing the semiconductor device
    5.
    发明申请
    Semiconductor device and method of manufacturing the semiconductor device 失效
    半导体装置及其制造方法

    公开(公告)号：US20070132021A1

    公开(公告)日：2007-06-14

    申请号：US11445181

    申请日：2006-06-02

    申请人： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Hirotaka Amasuga

    发明人： Tetsuo Kunii ,  Yoshitsugu Yamamoto ,  Hirotaka Amasuga

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7783 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66856 ,  H01L29/8128

    摘要： A semiconductor device includes a substrate having a recess, a gate electrode in the recess in the substrate, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. An insulating film is on at least on a surface of the gate electrode and a portion in the recess, other than where the gate electrode is located, and a shield electrode connected to the source electrode is located on a portion of the insulating film between the gate electrode and the drain electrode.

    摘要翻译： 半导体器件包括具有凹部的基板，在基板的凹部中的栅电极以及设置在栅电极的相对侧上的源电极和漏电极。 绝缘膜至少在栅电极的表面和凹部中的除了栅电极所在的部分之外的部分上，并且与源电极连接的屏蔽电极位于绝缘膜的一部分之间 栅电极和漏电极。

    Field-effect transistor and method of manufacturing the same
    6.
    发明授权
    Field-effect transistor and method of manufacturing the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US08063420B2

    公开(公告)日：2011-11-22

    申请号：US12512099

    申请日：2009-07-30

    申请人： Hirotaka Amasuga

    发明人： Hirotaka Amasuga

    IPC分类号： H01L29/80

    CPC分类号： H01L29/2003 ,  H01L29/0649 ,  H01L29/42316 ,  H01L29/7786 ,  H01L29/8128

    摘要： A field-effect transistor with improved moisture resistance without an increase in gate capacitance, and a method of manufacturing the field-effect transistor are provided. The field-effect transistor includes: a T-shaped gate electrode on a semiconductor layer; and a first highly moisture-resistant protective film including one of an insulating film and an organic film having high etching resistance, the first highly moisture-resistant protective film being located above the T-shaped gate electrode, over all of a region in which the T-shaped gate electrode is located. A cavity is located between the semiconductor layer and the first highly moisture-resistant protective film, below a canopy of the T-shaped gate electrode. An end surface of the cavity is closed by a second highly moisture-resistant film.

    摘要翻译： 提供一种具有改善的耐湿性而不增加栅极电容的场效应晶体管，以及制造场效应晶体管的方法。 场效应晶体管包括：半导体层上的T形栅电极; 以及第一高耐湿保护膜，其包括绝缘膜和具有高耐腐蚀性的有机膜之一，所述第一高耐湿保护膜位于所述T形栅电极的上方， T形栅电极位于。 空腔位于半导体层和第一高度防潮保护膜之间，位于T形栅电极的顶盖的下方。 空腔的端面由第二高度防潮的膜封闭。

    Semiconductor device
    7.
    发明申请
    Semiconductor device 审中-公开
    半导体器件

    公开(公告)号：US20060231871A1

    公开(公告)日：2006-10-19

    申请号：US11374141

    申请日：2006-03-14

    申请人： Hirotaka Amasuga ,  Toshihiko Shiga ,  Tetsuo Kunii ,  Tomoki Oku

    发明人： Hirotaka Amasuga ,  Toshihiko Shiga ,  Tetsuo Kunii ,  Tomoki Oku

    IPC分类号： H01L29/80 ,  H01L29/76 ,  H01L31/112 ,  H01L29/94 ,  H01L31/00

    CPC分类号： H01L29/475 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/42316

    摘要： A gate electrode serving as a Schottky electrode includes a TaNx layer and an Au layer. The TaNx layer serves as a barrier metal for preventing atoms from diffusing from the Au layer into a substrate. TaNx does not contain Si, and therefore has a higher humidity resistance than WSiN containing Si. Accordingly, the gate electrode has a higher humidity resistance than a conventional gate electrode including a WSiN layer. Setting a nitrogen content at less than 0.8 can prevent significant degradation in Schottky characteristics as compared to the conventional gate electrode. Setting the nitrogen content at 0.5 or less, Schottky characteristics can be improved more than in the conventional gate electrode.

    摘要翻译： 用作肖特基电极的栅电极包括TaNx层和Au层。 TaNx层用作防止原子从Au层扩散到衬底中的阻挡金属。 TaNx不含Si，因此具有比含有Si的WSiN更高的耐湿性。 因此，栅电极具有比包含WSiN层的常规栅电极更高的耐湿性。 与常规栅电极相比，氮含量小于0.8可以防止肖特基特性的显着降低。 将氮含量设定为0.5以下，与常规栅电极相比，肖特基特性可以得到改善。

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110006351A1

    公开(公告)日：2011-01-13

    申请号：US12828328

    申请日：2010-07-01

    申请人： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

    发明人： Tetsuo Kunii ,  Hirotaka Amasuga ,  Yoshitsugu Yamamoto ,  Youichi Nogami

    IPC分类号： H01L27/06 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L29/4238 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/812

    摘要： A semiconductor device includes: a semiconductor substrate; an impurity-doped region at a top surface of the semiconductor substrate; an insulating region located around the impurity-doped region on the top surface of the semiconductor substrate; a gate electrode on the impurity-doped region; a first electrode and a second electrode located on the impurity-doped region, sandwiching the gate electrode; a first pad located on the insulating region and connected to the gate electrode; a second pad facing the first pad across the impurity-doped region, on the insulating region, and connected to the second electrode; and a conductor located between the first electrode and the second pad on the insulating region.

    摘要翻译： 半导体器件包括：半导体衬底; 在所述半导体衬底的顶表面处的杂质掺杂区域; 绝缘区域，位于半导体衬底的顶表面上的杂质掺杂区域周围; 杂质掺杂区上的栅电极; 位于所述杂质掺杂区域上的第一电极和第二电极，夹着所述栅电极; 位于所述绝缘区域上并连接到所述栅电极的第一焊盘; 在所述绝缘区域上跨越所述杂质掺杂区域面对所述第一焊盘的第二焊盘，并且连接到所述第二电极; 以及位于绝缘区域上的第一电极和第二焊盘之间的导体。