公开(公告)号：US20160133706A1

公开(公告)日：2016-05-12

申请号：US14899032

申请日：2013-06-17

Applicant: HITACHI, LTD.

Inventor： Takashi Ishigaki ,  Ryuta Tsuchiya

IPC: H01L29/16 ,  H01L29/739 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/04 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/046 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7805 ,  H01L29/7813

Abstract: Provided is a vertical MOSFET in which a conduction deterioration phenomenon is prevented during a current return operation and an on-voltage is low during the current return operation. A semiconductor device includes a hole barrier region that is provided between a second-conductivity-type body region and a first-conductivity-type epitaxial layer below a second-conductivity-type body contact region and functions as a potential barrier to a hole which flows from a source electrode to the first-conductivity-type epitaxial layer through the second-conductivity-type body contact region and the second-conductivity-type body region.

Abstract translation: 提供了在电流返回操作期间防止导通劣化现象并且在当前返回操作期间导通电压低的垂直MOSFET。 半导体器件包括在第二导电型体区和位于第二导电型体接触区之下的第一导电型外延层之间的空穴阻挡区，并且作为流过孔的势垒 从源电极通过第二导电型体接触区域和第二导电型体区域到第一导电型外延层。

公开(公告)号：US20210326738A1

公开(公告)日：2021-10-21

申请号：US17206326

申请日：2021-03-19

Applicant: Hitachi, Ltd.

Inventor： Yusuke Kanno ,  Hiroyuki Mizuno ,  Ryuta Tsuchiya ,  Noriyuki Lee ,  Gou Shinkai ,  Tatsuya Tomaru

IPC: G06N10/00 ,  G06F9/38 ,  G06F17/18

Abstract: A quantum computer includes: a module including quantum computation units having a plurality of qubits and selection units that cause the quantum computation units to perform parallel computations; and a read unit that acquires computation results of the quantum computation units of a plurality of modules and performs statistical averaging on the plurality of acquired computation results.

公开(公告)号：US08710550B2

公开(公告)日：2014-04-29

申请号：US13665194

申请日：2012-10-31

Applicant: Hitachi, Ltd.

Inventor： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Kazuhiro Mochizuki ,  Akihisa Terano

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/00

CPC classification number: H01L29/4236 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787

Abstract: A semiconductor device includes a nitride semiconductor stack having at least two hetero junction bodies where a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer are disposed, and includes a drain electrode and, a source electrode disposed to the nitride semiconductor stack, and gate electrodes at a position put between the drain electrode and the source electrode and disposed so as to oppose them respectively in which the drain electrode and the source electrode are disposed over the surface or on the lateral side of the nitride semiconductor stack, and the gate electrode has a first gate electrode disposed in the direction of the depth of the nitride semiconductor stack and a second gate electrode disposed in the direction of the depth of the nitride semiconductor at a depth different from the first gate electrode.

Abstract translation: 半导体器件包括具有至少两个异质结体的氮化物半导体堆叠，其中设置具有比第一氮化物半导体层宽的带隙的第一氮化物半导体层和第二氮化物半导体层，并且包括漏电极， 设置在氮化物半导体堆叠上的源电极以及放置在漏电极和源电极之间的位置处的栅电极，并分别与漏电极和源电极配置在表面上或在其上 氮化物半导体堆叠的横向侧，并且栅电极具有沿氮化物半导体堆叠的深度方向设置的第一栅电极和沿氮化物半导体的深度方向设置的第二栅电极，其深度不同于 第一栅电极。

公开(公告)号：US09799734B2

公开(公告)日：2017-10-24

申请号：US14899032

申请日：2013-06-17

Applicant: HITACHI, LTD.

Inventor： Takashi Ishigaki ,  Ryuta Tsuchiya

IPC: H01L29/739 ,  H01L21/04 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/046 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7805 ,  H01L29/7813

Abstract: Provided is a vertical MOSFET in which a conduction deterioration phenomenon is prevented during a current return operation and an on-voltage is low during the current return operation. A semiconductor device includes a hole barrier region that is provided between a second-conductivity-type body region and a first-conductivity-type epitaxial layer below a second-conductivity-type body contact region and functions as a potential barrier to a hole which flows from a source electrode to the first-conductivity-type epitaxial layer through the second-conductivity-type body contact region and the second-conductivity-type body region.

公开(公告)号：US09263571B2

公开(公告)日：2016-02-16

申请号：US14651555

申请日：2012-12-28

Applicant: HITACHI, LTD.

Inventor： Ryuta Tsuchiya ,  Hiroyuki Matsushima ,  Naoki Tega ,  Digh Hisamoto

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L21/02529 ,  H01L21/0485 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7813

Abstract: When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time.

Abstract translation: 为了降低SiC DOMSFET中的导通电阻而减小栅极长度，难以同时通过栅极长度的降低和高的元件耐受电压来实现导通电阻的降低。 在本发明中，在形成源极扩散层区域之后形成体层，然后使源极扩散层区域的一部分凹陷。 由于体层的存在，可以增大源极扩散区域和各个端部之间的距离，有效地扩大耗尽层，并且可以抑制端部的电场浓度，从而提高耐电压特性。 因此，本发明可以提供通过同时降低栅极长度和高元件耐受电压来实现沟道电阻降低的碳化硅半导体器件。

公开(公告)号：US12169759B2

公开(公告)日：2024-12-17

申请号：US17630266

申请日：2020-03-12

Applicant: Hitachi, Ltd.

Inventor： Noriyuki Lee ,  Ryuta Tsuchiya ,  Digh Hisamoto

IPC: G06N10/40

Abstract: The first layer includes a first gate electrode array disposed in the first direction to control the qubits of the qubit string, and a second gate electrode array disposed in the first direction to control the inter-qubit interaction of the interaction string. The second layer includes a third gate electrode array disposed in the second direction, and a fourth gate electrode array disposed in the second direction adjacently to the third gate electrode array. The third and the fourth gate electrode arrays control a part of the multiple qubits, and a part of the multiple inter-qubit interactions, respectively.

公开(公告)号：US09941430B2

公开(公告)日：2018-04-10

申请号：US15442113

申请日：2017-02-24

Applicant: HITACHI, LTD.

Inventor： Aleksey Andreev ,  David Williams ,  Ryuta Tsuchiya ,  Yuji Suwa

IPC: H01L29/06 ,  H01L31/0352 ,  H01L31/028 ,  H01L31/024 ,  H01L33/06 ,  H01L33/34 ,  H01L33/64 ,  H01L31/112 ,  H01L33/00 ,  G06N99/00 ,  B82Y10/00 ,  B82Y20/00

CPC classification number: H01L31/035218 ,  B82Y10/00 ,  B82Y15/00 ,  B82Y20/00 ,  B82Y30/00 ,  G06N99/002 ,  H01L29/0649 ,  H01L29/127 ,  H01L29/66977 ,  H01L29/7613 ,  H01L31/024 ,  H01L31/028 ,  H01L31/112 ,  H01L33/0041 ,  H01L33/06 ,  H01L33/34 ,  H01L33/64 ,  Y10S977/774 ,  Y10S977/814 ,  Y10S977/933 ,  Y10S977/95 ,  Y10S977/954

Abstract: A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers.

公开(公告)号：US09825166B2

公开(公告)日：2017-11-21

申请号：US14760166

申请日：2013-01-23

Applicant: HITACHI, LTD.

Inventor： Naoki Tega ,  Digh Hisamoto ,  Satoru Akiyama ,  Takashi Takahama ,  Tadao Morimoto ,  Ryuta Tsuchiya

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L21/04 ,  H01L29/66 ,  H01L29/08 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7813 ,  H01L21/02529 ,  H01L21/047 ,  H01L21/26513 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7811

Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.

公开(公告)号：US09029979B2

公开(公告)日：2015-05-12

申请号：US13684314

申请日：2012-11-23

Applicant: Hitachi, Ltd.

Inventor： Hiroyuki Yoshimoto ,  Ryuta Tsuchiya ,  Naoki Tega ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yuki Mori

IPC: H01L21/70 ,  H01L29/16 ,  H01L21/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/1608 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7827

Abstract: A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.

Abstract translation: 形成沟槽，在（0001）面4h-SiC半导体元件的沟道区的周围埋置氧化硅膜。 沟槽中的氧化膜以这样的平面布局限定，使得沿着c轴的方向施加拉伸应变，并且沿着与c轴垂直的平面上的两个或更多个轴施加压缩应变。 例如，埋置有氧化物膜的沟槽沟可以被配置为使得它们处于围绕通道的三角形状，或者当离散布置时相对于通道对称地布置为中心。