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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20120032246A1

    公开(公告)日：2012-02-09

    申请号：US13196084

    申请日：2011-08-02

    申请人： Masashi HONDA ,  Hitoshi Ito ,  Hideyuki Kinoshita

    发明人： Masashi HONDA ,  Hitoshi Ito ,  Hideyuki Kinoshita

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/7881 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/40114

    摘要： A nonvolatile semiconductor memory device according to an embodiment includes a semiconductor substrate, a memory cell transistor formed in a memory cell region, and a field-effect transistor formed in a peripheral circuit region. The memory cell transistor includes: a floating gate electrode; a first inter-electrode insulating film; and a control gate electrode. The field-effect transistor includes: a lower gate electrode; a second inter-electrode insulating film having an opening; and an upper gate electrode electrically connected to the lower gate electrode via the opening. The control gate electrode and the upper gate electrode are formed by a plurality of conductive films that are stacked. The control gate electrode and the upper gate electrode include a barrier film formed in one of interfaces between the stacked conductive films and configured to suppress diffusion of metal atoms. The control gate electrode and the upper gate electrode have a part that is silicided.

    摘要翻译： 根据实施例的非易失性半导体存储器件包括形成在存储单元区域中的半导体衬底，存储单元晶体管和形成在外围电路区域中的场效应晶体管。 存储单元晶体管包括：浮栅电极; 第一电极间绝缘膜; 和控制栅电极。 场效应晶体管包括：下栅电极; 具有开口的第二电极间绝缘膜; 以及通过所述开口电连接到所述下栅电极的上栅电极。 控制栅极电极和上部栅极电极由堆叠的多个导电膜形成。 控制栅电极和上栅电极包括形成在层叠导电膜之间的界面之一中的阻挡膜，并且被构造成抑制金属原子的扩散。 控制栅极电极和上部栅电极具有被硅化的部分。

    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    非挥发性半导体存储器件及其制造方法

    公开(公告)号：US20100096682A1

    公开(公告)日：2010-04-22

    申请号：US12556242

    申请日：2009-09-09

    申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

    发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Akihiro Nitayama ,  Hideaki Aochi ,  Hitoshi Ito ,  Yasuyuki Matsuoka

    IPC分类号： H01L29/78 ,  H01L21/768

    CPC分类号： H01L27/11578 ,  H01L27/11565 ,  H01L27/11582

    摘要： A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction.

    摘要翻译： 非易失性半导体存储装置具有串联连接的多个电可重写存储单元的存储串。 非挥发性半导体存储装置还具有形成为相对于基板向上突出的突出层。 存储器串包括：层叠在基板上的多个第一导电层; 形成为穿透所述多个第一导电层的第一半导体层; 以及形成在第一导电层和第一半导体层之间的电荷存储层，并且能够存储电荷。 多个第一导电层中的每一个包括：平行于基板延伸的底部; 以及沿底部的突出层相对于基板向上延伸的侧部。 该突出层在平行于基板的第一方向上的宽度小于或等于其在层叠方向上的长度。

    Semiconductor device having elevated source/drain on source region and drain region
    10.
    发明授权
    Semiconductor device having elevated source/drain on source region and drain region 失效
    在源极区和漏极区具有升高的源极/漏极的半导体器件

    公开(公告)号：US07190035B2

    公开(公告)日：2007-03-13

    申请号：US10802758

    申请日：2004-03-18

    申请人： Hitoshi Ito

    发明人： Hitoshi Ito

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/66628 ,  H01L21/76224 ,  H01L21/823481

    摘要： A semiconductor device disclosed herein comprises: an element isolation insulator which is formed on the surface side of a semiconductor substrate to provide electrical insulation from other elements, a height of a surface of the element isolation insulator being equal to or lower than that of a surface of the semiconductor substrate; a stopper which is formed of a material different from that of the element isolation insulator and which is at a predetermined distance from the semiconductor substrate so as to protrude from the surface of the element isolation insulator; and an elevated source/drain which is formed on a source region and a drain region so as to be elevated from the surface of the semiconductor substrate.

    摘要翻译： 本文公开的半导体器件包括：元件隔离绝缘体，其形成在半导体衬底的表面侧以提供与其它元件的电绝缘，元件隔离绝缘体的表面的高度等于或低于表面的高度 的半导体衬底; 阻挡件，其由与所述元件隔离绝缘体的材料不同的材料形成，并且距所述半导体基板预定距离，以从所述元件隔离绝缘体的表面突出; 以及形成在源极区域和漏极区域上以从半导体衬底的表面升高的源极/漏极的升高。