利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.015 秒)

    Laser ablation to selectively thin wafers/die to lower device RDSON
    1.
    发明申请
    Laser ablation to selectively thin wafers/die to lower device RDSON 有权
    激光烧蚀选择性薄晶片/裸片降低器件RDSON

    公开(公告)号：US20070210407A1

    公开(公告)日：2007-09-13

    申请号：US11636762

    申请日：2006-12-11

    申请人： Hugo Burke ,  Robert Montgomery

    发明人： Hugo Burke ,  Robert Montgomery

    IPC分类号： H01L29/00

    CPC分类号： H01L21/306 ,  H01L21/78 ,  Y10S438/977

    摘要： A laser ablated wafer for a semiconductor device, such as a MOSFET or other power device, and a method of producing such a wafer to achieve a lower electrical resistance are provided. The method includes forming first holes, slots or trenches on a first surface of the wafer and focusing a laser beam to form second trenches on a bottom surface of the wafer, and filling the trenches, for example using aluminum or other metallic filling, to provide conductive electrodes or conductive surfaces for the semiconductor device. In such a wafer each trench on the second surface may be deeper, for example hundreds of microns deep and tens of microns wide.

    摘要翻译： 提供了用于诸如MOSFET或其他功率器件的半导体器件的激光烧蚀晶片，以及制造这样的晶片以实现较低电阻的方法。 该方法包括在晶片的第一表面上形成第一孔，槽或沟槽，并聚焦激光束以在晶片的底表面上形成第二沟槽，并且例如使用铝或其它金属填充物填充沟槽，以提供 导电电极或用于半导体器件的导电表面。 在这种晶片中，第二表面上的每个沟槽可以更深，例如几百微米深和几十微米宽。

    Method for fabricating a shallow and narrow trench FETand related structures
    7.
    发明申请
    Method for fabricating a shallow and narrow trench FETand related structures 有权
    制造浅沟槽窄沟槽FET及相关结构的方法

    公开(公告)号：US20110284950A1

    公开(公告)日：2011-11-24

    申请号：US12800662

    申请日：2010-05-20

    申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan

    发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L21/265 ,  H01L21/30625 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

    摘要： Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

    摘要翻译： 公开了一种制造浅沟槽场效应晶体管（沟槽FET）的方法。 该方法包括在第一导电类型的半导体衬底内形成沟槽，沟槽包括侧壁和底部。 该方法还包括在沟槽中形成基本上均匀的栅极电介质，以及在所述沟槽内和所述栅极电介质上方形成栅电极。 该方法还包括在形成沟槽之后掺杂半导体衬底以形成第二导电类型的沟道区。 在一个实施例中，在形成栅极电介质之后并在形成栅电极之后执行掺杂步骤。 在另一个实施例中，掺杂步骤在形成栅极电介质之后，但在形成栅电极之前进行。 还公开了通过本发明方法形成的结构。

    Power semiconductor device
    9.
    发明申请
    Power semiconductor device 有权
    功率半导体器件

    公开(公告)号：US20060286732A1

    公开(公告)日：2006-12-21

    申请号：US11449940

    申请日：2006-06-09

    申请人： Hugo Burke ,  Simon Green

    发明人： Hugo Burke ,  Simon Green

    IPC分类号： H01L21/8234 ,  H01L29/76 ,  G01F1/58

    CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41766

    摘要： A power semiconductor device that includes a plurality of gate structure each having a gate insulation of a first thickness, and a termination region, the termination including a field insulation body surrounding the active region and having a recess that includes a bottom insulation thicker than the first thickness.

    摘要翻译： 一种功率半导体器件，其包括各自具有第一厚度的栅极绝缘体的多个栅极结构和端接区域，所述端子包括围绕所述有源区域的场绝缘体，并且具有凹部，所述凹部包括比所述第一厚度更厚的底部绝缘体 厚度。