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公开(公告)号:US20170186733A1
公开(公告)日:2017-06-29
申请号:US15457744
申请日:2017-03-13
发明人: Vikas Dubey , Ingrid De Wolf , Eric Beyne
IPC分类号: H01L25/065 , H01L25/00 , H01L23/31 , H01L23/00 , H01L23/528
CPC分类号: H01L25/0657 , H01L23/3157 , H01L23/3192 , H01L23/528 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/80 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/0213 , H01L2224/0214 , H01L2224/02145 , H01L2224/0217 , H01L2224/02175 , H01L2224/0218 , H01L2224/02185 , H01L2224/0224 , H01L2224/0225 , H01L2224/02255 , H01L2224/0401 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/0903 , H01L2224/10135 , H01L2224/10145 , H01L2224/10165 , H01L2224/10175 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/80004 , H01L2224/80007 , H01L2224/80121 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80203 , H01L2224/80894 , H01L2224/80907 , H01L2224/81002 , H01L2224/81007 , H01L2224/81121 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/81894 , H01L2224/81907 , H01L2224/83143 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014
摘要: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.
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公开(公告)号:US09799632B2
公开(公告)日:2017-10-24
申请号:US15457744
申请日:2017-03-13
发明人: Vikas Dubey , Ingrid De Wolf , Eric Beyne
IPC分类号: H01L23/02 , H01L25/065 , H01L23/00 , H01L23/528 , H01L23/31 , H01L25/00
CPC分类号: H01L25/0657 , H01L23/3157 , H01L23/3192 , H01L23/528 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/80 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/0213 , H01L2224/0214 , H01L2224/02145 , H01L2224/0217 , H01L2224/02175 , H01L2224/0218 , H01L2224/02185 , H01L2224/0224 , H01L2224/0225 , H01L2224/02255 , H01L2224/0401 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/0903 , H01L2224/10135 , H01L2224/10145 , H01L2224/10165 , H01L2224/10175 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/80004 , H01L2224/80007 , H01L2224/80121 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80203 , H01L2224/80894 , H01L2224/80907 , H01L2224/81002 , H01L2224/81007 , H01L2224/81121 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/81894 , H01L2224/81907 , H01L2224/83143 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014
摘要: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.
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公开(公告)号:US09601459B2
公开(公告)日:2017-03-21
申请号:US14576637
申请日:2014-12-19
发明人: Vikas Dubey , Ingrid De Wolf , Eric Beyne
IPC分类号: H01L29/80 , H01L23/00 , H01L25/065 , H01L25/00
CPC分类号: H01L25/0657 , H01L23/3157 , H01L23/3192 , H01L23/528 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/80 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/0213 , H01L2224/0214 , H01L2224/02145 , H01L2224/0217 , H01L2224/02175 , H01L2224/0218 , H01L2224/02185 , H01L2224/0224 , H01L2224/0225 , H01L2224/02255 , H01L2224/0401 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/0903 , H01L2224/10135 , H01L2224/10145 , H01L2224/10165 , H01L2224/10175 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/80004 , H01L2224/80007 , H01L2224/80121 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80203 , H01L2224/80894 , H01L2224/80907 , H01L2224/81002 , H01L2224/81007 , H01L2224/81121 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/81894 , H01L2224/81907 , H01L2224/83143 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014
摘要: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.
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公开(公告)号:US20150179605A1
公开(公告)日:2015-06-25
申请号:US14576637
申请日:2014-12-19
发明人: Vikas Dubey , Ingrid De Wolf , Eric Beyne
IPC分类号: H01L23/00
CPC分类号: H01L25/0657 , H01L23/3157 , H01L23/3192 , H01L23/528 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/09 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/33 , H01L24/80 , H01L24/81 , H01L24/83 , H01L25/50 , H01L2224/0213 , H01L2224/0214 , H01L2224/02145 , H01L2224/0217 , H01L2224/02175 , H01L2224/0218 , H01L2224/02185 , H01L2224/0224 , H01L2224/0225 , H01L2224/02255 , H01L2224/0401 , H01L2224/05647 , H01L2224/08145 , H01L2224/08225 , H01L2224/0903 , H01L2224/10135 , H01L2224/10145 , H01L2224/10165 , H01L2224/10175 , H01L2224/13147 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/80004 , H01L2224/80007 , H01L2224/80121 , H01L2224/8013 , H01L2224/80132 , H01L2224/80143 , H01L2224/80203 , H01L2224/80894 , H01L2224/80907 , H01L2224/81002 , H01L2224/81007 , H01L2224/81121 , H01L2224/8113 , H01L2224/81132 , H01L2224/81141 , H01L2224/81143 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/81894 , H01L2224/81907 , H01L2224/83143 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014
摘要: Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid.
摘要翻译: 第一微电子部件与第二微电子部件的接收表面的对准通过与静电取向相结合的毛细管力诱导的自对准来实现。 后者通过沿着第一部件的周边提供至少一个第一电导体线,以及沿着第二部件的接收表面上的位置的周边的至少一个第二电导体,部件将放置在其上 。 由导体线包围的接触区域被润湿层覆盖。 电导体线可以嵌入沿着周边延伸的防湿材料条,以产生润湿性对比度。 润湿性对比度有助于保持接触区域之间的取向液滴,从而通过毛细管力获得自对准。 通过在导体线上施加适当的电荷,实现静电自对准,这改善了通过毛细管力获得的对准并且在液体的蒸发期间保持对准。
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公开(公告)号:US11367705B2
公开(公告)日:2022-06-21
申请号:US16719680
申请日:2019-12-18
申请人: IMEC VzW
发明人: Eric Beyne
IPC分类号: H01L23/00 , H01L21/56 , H01L21/66 , H01L25/065 , H01L25/00
摘要: A method of using sacrificial structures in a mold substrate for packaging a first die and one or more second dies or stacks thereof is disclosed. The method allows testing of the first die prior to mounting the second dies, without requiring a TSV insert. In one aspect, a block of sacrificial material is embedded together with the first die in a first mold substrate and to one side of the first die. The removal of the block creates an opening. The method is configured so that contacts are exposed at the bottom of the opening, the contacts being electrically connected to corresponding contacts on the first die. This may be realized by bonding both the die and the sacrificial block to a redistribution layer, or by mounting a bridge device between the first die and the block prior to a first overmolding applied for producing the first mold substrate. A second die or a stack of second dies is mounted in the opening and bonded to the exposed contacts, after which a second mold substrate is produced, embedding the second die or dies.
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公开(公告)号:US20210098299A1
公开(公告)日:2021-04-01
申请号:US17038737
申请日:2020-09-30
申请人: IMEC VZW
发明人: Frank Holsteyns , Eric Beyne , Christophe Lorant , Simon Braun
摘要: A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.
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公开(公告)号:US10797016B2
公开(公告)日:2020-10-06
申请号:US15798939
申请日:2017-10-31
发明人: Vikas Dubey , Eric Beyne , Giovanni Capuz
IPC分类号: H01L23/00
摘要: A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.
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公开(公告)号:US10141284B2
公开(公告)日:2018-11-27
申请号:US15604454
申请日:2017-05-24
申请人: IMEC VZW
发明人: Soon-Wook Kim , Lan Peng , Patrick Verdonck , Robert Miller , Gerald Peter Beyer , Eric Beyne
IPC分类号: H01L23/00 , H01L23/31 , H01L25/065 , H01L21/02 , H01L21/3105
摘要: The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.
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公开(公告)号:US20180247914A1
公开(公告)日:2018-08-30
申请号:US15908641
申请日:2018-02-28
申请人: IMEC VZW
发明人: Lan Peng , Soon-Wook Kim , Eric Beyne , Gerald Peter Beyer , Erik Sleeckx , Robert Miller
IPC分类号: H01L23/00 , H01L23/522 , H01L23/528
CPC分类号: H01L24/83 , H01J37/32091 , H01J37/321 , H01J2237/334 , H01L21/2007 , H01L23/5226 , H01L23/528 , H01L24/29 , H01L24/32 , H01L2224/29082 , H01L2224/29187 , H01L2224/32145 , H01L2224/83009 , H01L2224/83011 , H01L2224/83022 , H01L2224/83895 , H01L2224/83896 , H01L2224/83948 , H01L2224/83986 , H01L2924/04642 , H01L2924/059 , H01L2924/20106 , H01L2924/20107
摘要: The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient. The method additionally includes bonding the first and the second substrates by contacting the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate to form a substrate assembly. The method further includes post-bond annealing the assembly.
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公开(公告)号:US11476162B2
公开(公告)日:2022-10-18
申请号:US17038737
申请日:2020-09-30
申请人: IMEC VZW
发明人: Frank Holsteyns , Eric Beyne , Christophe Lorant , Simon Braun
摘要: A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.
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